Re: [PATCH 6.6.y] serial: 8250_pxa: Configure tx_loadsz to match FIFO IRQ level

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On Tue, Jun 18, 2024 at 07:09:29PM -0700, Doug Brown wrote:
> The FIFO is 64 bytes, but the FCR is configured to fire the TX interrupt
> when the FIFO is half empty (bit 3 = 0). Thus, we should only write 32
> bytes when a TX interrupt occurs.
> 
> This fixes a problem observed on the PXA168 that dropped a bunch of TX
> bytes during large transmissions.
> 
> Fixes: ab28f51c77cd ("serial: rewrite pxa2xx-uart to use 8250_core")
> Signed-off-by: Doug Brown <doug@xxxxxxxxxxxxx>
> Link: https://lore.kernel.org/r/20240519191929.122202-1-doug@xxxxxxxxxxxxx
> Cc: stable <stable@xxxxxxxxxx>
> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
> (cherry picked from commit 5208e7ced520a813b4f4774451fbac4e517e78b2)
> Signed-off-by: Doug Brown <doug@xxxxxxxxxxxxx>
> ---
>  drivers/tty/serial/8250/8250_pxa.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/tty/serial/8250/8250_pxa.c b/drivers/tty/serial/8250/8250_pxa.c
> index a5b3ea27fc90..2cbaf68d2811 100644
> --- a/drivers/tty/serial/8250/8250_pxa.c
> +++ b/drivers/tty/serial/8250/8250_pxa.c
> @@ -124,6 +124,7 @@ static int serial_pxa_probe(struct platform_device *pdev)
>  	uart.port.regshift = 2;
>  	uart.port.irq = irq;
>  	uart.port.fifosize = 64;
> +	uart.tx_loadsz = 32;
>  	uart.port.flags = UPF_IOREMAP | UPF_SKIP_TEST | UPF_FIXED_TYPE;
>  	uart.port.dev = &pdev->dev;
>  	uart.port.uartclk = clk_get_rate(data->clk);
> -- 
> 2.34.1
> 
>

All now queued up, thanks.

greg k-h




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