[request for stable inclusion]

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hi gerg,

Now on IvyBridge machines with 3.10 stable, perf could not get proper dTLB-load-misses event when performing "perf stat -e dTLB-load-misses
sleep 1", which outputs:

Performance counter stats for 'sleep 1':
0 dTLB-load-misses
1.000951106 seconds time elapsed

0 dTLB-load-misses means we fail to get the dTLB-load-misses event. Upstream patch 1996388e explains the result and fix the bug. I have already test the patch, by which I can get proper dTLB-load-misses on my IvyBridge machine:

272 dTLB-load-misses

So, I suggest cherry-picking it to 3.10-stable tree.

the commit is 1996388e9f4e3444db8273bc08d25164d2967c21 as follows:

------------------------------------------------------------------------
commit 1996388e9f4e3444db8273bc08d25164d2967c21
Author: Vince Weaver <vincent.weaver@xxxxxxxxx>
Date:   Mon Jul 14 15:33:25 2014 -0400

    perf/x86/intel: Use proper dTLB-load-misses event on IvyBridge

    This was discussed back in February:

        https://lkml.org/lkml/2014/2/18/956

    But I never saw a patch come out of it.

    On IvyBridge we share the SandyBridge cache event tables, but the
    dTLB-load-miss event is not compatible.  Patch it up after
    the fact to the proper DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK

    Signed-off-by: Vince Weaver <vincent.weaver@xxxxxxxxx>
    Signed-off-by: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
    Cc: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>
    Cc: Linus Torvalds <torvalds@xxxxxxxxxxxxxxxxxxxx>
Link: http://lkml.kernel.org/r/alpine.DEB.2.11.1407141528200.17214@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
    Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 07846d7..c206815 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2474,6 +2474,9 @@ __init int intel_pmu_init(void)
    case 62: /* IvyBridge EP */
        memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
               sizeof(hw_cache_event_ids));
+       /* dTLB-load-misses on IVB is different than SNB */
+ hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
+
        memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
               sizeof(hw_cache_extra_regs));


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