On Wed, 08 Oct 2014, Paulo Zanoni <przanoni@xxxxxxxxx> wrote: > From: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > > We were missing the pipe B/C vblank bits! Take a look at > gen8_de_irq_postinstall for a comparison. > > This should fix a bunch of IGT tests. > > There are a few more things we could improve on this code, but this > should be the minimal fix to unblock us. > > v2: s/extra_iir/extra_ier/ because IIR doesn't make sense (Ville) > > Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=83640 Maybe https://bugs.freedesktop.org/show_bug.cgi?id=84217 too, and others? BR, Jani. > Testcase: igt/* > Cc: stable@xxxxxxxxxxxxxxx > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_irq.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index b12c4c4..c141ff8 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -3166,11 +3166,13 @@ static void gen8_irq_reset(struct drm_device *dev) > > void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) > { > + uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; > + > spin_lock_irq(&dev_priv->irq_lock); > GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], > - ~dev_priv->de_irq_mask[PIPE_B]); > + ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); > GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], > - ~dev_priv->de_irq_mask[PIPE_C]); > + ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); > spin_unlock_irq(&dev_priv->irq_lock); > } > > -- > 2.1.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html