Hi stable maintainers,
These two patches: c149dcb5c60bfea8871f16dfcc0690255eeb825f
drm/i915: provide interface for audio driver to query cdclk
and
e4d9e513dedb5ac4e166c1053314fa935ddecc8c
ALSA: hda - restore BCLK M/N value as per CDCLK for HSW/BDW display HDA
controller
...never seem to have made it into 3.12+ stable kernels. They fix an
issue where playback rate over Haswell HDMI audio can be faster than normal.
Now, the latter of these two patches requires a restructure of moving
things from hda_intel.c to hda_priv.h, which looked tedious and
potentially error-prone to backport in itself, so instead I rewrote the
function slightly, see attachment.
Do you think this is a reasonable approach?
Note: It is possible that the patches in its current form do not apply
cleanly if the stable kernel is missing another stable patch
(a07187c992be945ab561b370cbb49cfd72064c3c
ALSA: hda - restore BCLK M/N values when resuming HSW/BDW display
controller), which is now superseded with this patch.
--
David Henningsson, Canonical Ltd.
https://launchpad.net/~diwic
>From a58fc03a2388433dac99333c488600cdcf9cde66 Mon Sep 17 00:00:00 2001
From: Jani Nikula <jani.nikula@xxxxxxxxx>
Date: Fri, 4 Jul 2014 10:00:37 +0800
Subject: [PATCH 1/2] drm/i915: provide interface for audio driver to query
cdclk
For Haswell and Broadwell, if the display power well has been disabled,
the display audio controller divider values EM4 M VALUE and EM5 N VALUE
will have been lost. The CDCLK frequency is required for reprogramming them
to generate 24MHz HD-A link BCLK. So provide a private interface for the
audio driver to query CDCLK.
This is a stopgap solution until a more generic interface between audio
and display drivers has been implemented.
Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
Reviewed-by: Damien Lespiau <damien.lespiau@xxxxxxxxx>
Signed-off-by: Mengdong Lin <mengdong.lin@xxxxxxxxx>
Cc: <stable@xxxxxxxxxxxxxxx>
Signed-off-by: Takashi Iwai <tiwai@xxxxxxx>
(backported from commit c149dcb5c60bfea8871f16dfcc0690255eeb825f)
Signed-off-by: David Henningsson <david.henningsson@xxxxxxxxxxxxx>
Conflicts:
drivers/gpu/drm/i915/intel_pm.c
include/drm/i915_powerwell.h
---
drivers/gpu/drm/i915/intel_pm.c | 21 +++++++++++++++++++++
include/drm/i915_powerwell.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1218c44..7b6bf30 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5882,6 +5882,27 @@ void i915_release_power_well(void)
}
EXPORT_SYMBOL_GPL(i915_release_power_well);
+/*
+ * Private interface for the audio driver to get CDCLK in kHz.
+ *
+ * Caller must request power well using i915_request_power_well() prior to
+ * making the call.
+ */
+int i915_get_cdclk_freq(void)
+{
+ struct drm_i915_private *dev_priv;
+
+ if (!hsw_pwr)
+ return -ENODEV;
+
+ dev_priv = container_of(hsw_pwr, struct drm_i915_private,
+ power_domains);
+
+ return intel_ddi_get_cdclk_freq(dev_priv);
+}
+EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
+
+
int intel_power_domains_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/include/drm/i915_powerwell.h b/include/drm/i915_powerwell.h
index cfdc884..d715ca1 100644
--- a/include/drm/i915_powerwell.h
+++ b/include/drm/i915_powerwell.h
@@ -32,5 +32,6 @@
/* For use by hda_i915 driver */
extern void i915_request_power_well(void);
extern void i915_release_power_well(void);
+extern int i915_get_cdclk_freq(void);
#endif /* _I915_POWERWELL_H_ */
--
1.9.1
>From e5d8a65599cf371d394ca157f466ab976513bff4 Mon Sep 17 00:00:00 2001
From: Mengdong Lin <mengdong.lin@xxxxxxxxx>
Date: Thu, 3 Jul 2014 17:02:23 +0800
Subject: [PATCH 2/2] ALSA: hda - restore BCLK M/N value as per CDCLK for
HSW/BDW display HDA controller
For HSW/BDW display HD-A controller, hda_set_bclk() is defined to set BCLK
by programming the M/N values as per the core display clock (CDCLK) queried from
i915 display driver.
And the audio driver will also set BCLK in azx_first_init() since the display
driver can turn off the shared power in boot phase if only eDP is connected
and M/N values will be lost and must be reprogrammed.
Signed-off-by: Mengdong Lin <mengdong.lin@xxxxxxxxx>
Cc: <stable@xxxxxxxxxxxxxxx>
Signed-off-by: Takashi Iwai <tiwai@xxxxxxx>
(backported from commit e4d9e513dedb5ac4e166c1053314fa935ddecc8c)
Signed-off-by: David Henningsson <david.henningsson@xxxxxxxxxxxxx>
Conflicts:
sound/pci/hda/hda_i915.c
sound/pci/hda/hda_i915.h
sound/pci/hda/hda_intel.c
---
sound/pci/hda/hda_i915.c | 55 +++++++++++++++++++++++++++++++++++++++++++++++
sound/pci/hda/hda_i915.h | 2 ++
sound/pci/hda/hda_intel.c | 48 +++++++++++++++--------------------------
3 files changed, 74 insertions(+), 31 deletions(-)
diff --git a/sound/pci/hda/hda_i915.c b/sound/pci/hda/hda_i915.c
index 76c13d5..ef03bf7 100644
--- a/sound/pci/hda/hda_i915.c
+++ b/sound/pci/hda/hda_i915.c
@@ -22,8 +22,17 @@
#include <drm/i915_powerwell.h>
#include "hda_i915.h"
+/* Intel HSW/BDW display HDA controller Extended Mode registers.
+ * EM4 (M value) and EM5 (N Value) are used to convert CDClk (Core Display
+ * Clock) to 24MHz BCLK: BCLK = CDCLK * M / N
+ * The values will be lost when the display power well is disabled.
+ */
+#define ICH6_REG_EM4 0x100c
+#define ICH6_REG_EM5 0x1010
+
static void (*get_power)(void);
static void (*put_power)(void);
+static int (*get_cdclk)(void);
void hda_display_power(bool enable)
{
@@ -38,6 +47,44 @@ void hda_display_power(bool enable)
put_power();
}
+bool haswell_get_bclk(unsigned int *m, unsigned int *n)
+{
+ int cdclk_freq;
+ unsigned int bclk_m, bclk_n;
+
+ if (!get_cdclk)
+ return false;
+
+ cdclk_freq = get_cdclk();
+ switch (cdclk_freq) {
+ case 337500:
+ bclk_m = 16;
+ bclk_n = 225;
+ break;
+
+ case 450000:
+ default: /* default CDCLK 450MHz */
+ bclk_m = 4;
+ bclk_n = 75;
+ break;
+
+ case 540000:
+ bclk_m = 4;
+ bclk_n = 90;
+ break;
+
+ case 675000:
+ bclk_m = 8;
+ bclk_n = 225;
+ break;
+ }
+
+ *m = bclk_m;
+ *n = bclk_n;
+ return true;
+}
+
+
int hda_i915_init(void)
{
int err = 0;
@@ -55,6 +102,10 @@ int hda_i915_init(void)
return -ENODEV;
}
+ get_cdclk = symbol_request(i915_get_cdclk_freq);
+ if (!get_cdclk) /* may have abnormal BCLK and audio playback rate */
+ pr_warn("hda-i915: get_cdclk symbol get fail\n");
+
snd_printd("HDA driver get symbol successfully from i915 module\n");
return err;
@@ -70,6 +121,10 @@ int hda_i915_exit(void)
symbol_put(i915_release_power_well);
put_power = NULL;
}
+ if (get_cdclk) {
+ symbol_put(i915_get_cdclk_freq);
+ get_cdclk = NULL;
+ }
return 0;
}
diff --git a/sound/pci/hda/hda_i915.h b/sound/pci/hda/hda_i915.h
index 5a63da2..0d435bd 100644
--- a/sound/pci/hda/hda_i915.h
+++ b/sound/pci/hda/hda_i915.h
@@ -18,10 +18,12 @@
#ifdef CONFIG_SND_HDA_I915
void hda_display_power(bool enable);
+bool haswell_get_bclk(unsigned int *m, unsigned int *n);
int hda_i915_init(void);
int hda_i915_exit(void);
#else
static inline void hda_display_power(bool enable) {}
+static inline bool haswell_get_bclk(unsigned int *m, unsigned int *n) { return false; }
static inline int hda_i915_init(void)
{
return -ENODEV;
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index e8de8a3..20c650e 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -673,10 +673,6 @@ static char *driver_short_names[] = {
struct hda_intel {
struct azx chip;
-
- /* HSW/BDW display HDA controller to restore BCLK from CDCLK */
- unsigned int bclk_m;
- unsigned int bclk_n;
};
/*
@@ -711,6 +707,15 @@ struct hda_intel {
/* for pcm support */
#define get_azx_dev(substream) (substream->runtime->private_data)
+static void haswell_set_bclk(struct azx *chip)
+{
+ unsigned int bclk_m, bclk_n;
+ if (haswell_get_bclk(&bclk_m, &bclk_n)) {
+ azx_writew(chip, EM4, bclk_m);
+ azx_writew(chip, EM5, bclk_n);
+ }
+}
+
#ifdef CONFIG_X86
static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
{
@@ -2922,22 +2927,6 @@ static int param_set_xint(const char *val, const struct kernel_param *kp)
#define azx_del_card_list(chip) /* NOP */
#endif /* CONFIG_PM */
-static void haswell_save_bclk(struct azx *chip)
-{
- struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
-
- hda->bclk_m = azx_readw(chip, EM4);
- hda->bclk_n = azx_readw(chip, EM5);
-}
-
-static void haswell_restore_bclk(struct azx *chip)
-{
- struct hda_intel *hda = container_of(chip, struct hda_intel, chip);
-
- azx_writew(chip, EM4, hda->bclk_m);
- azx_writew(chip, EM5, hda->bclk_n);
-}
-
#if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
/*
* power management
@@ -2965,12 +2954,6 @@ static int azx_suspend(struct device *dev)
chip->irq = -1;
}
- /* Save BCLK M/N values before they become invalid in D3.
- * Will test if display power well can be released now.
- */
- if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
- haswell_save_bclk(chip);
-
if (chip->msi)
pci_disable_msi(chip->pci);
pci_disable_device(pci);
@@ -2992,7 +2975,7 @@ static int azx_resume(struct device *dev)
if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
hda_display_power(true);
- haswell_restore_bclk(chip);
+ haswell_set_bclk(chip);
}
pci_set_power_state(pci, PCI_D0);
pci_restore_state(pci);
@@ -3037,10 +3020,9 @@ static int azx_runtime_suspend(struct device *dev)
azx_stop_chip(chip);
azx_enter_link_reset(chip);
azx_clear_irq_pending(chip);
- if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
- haswell_save_bclk(chip);
+ if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
hda_display_power(false);
- }
+
return 0;
}
@@ -3060,7 +3042,7 @@ static int azx_runtime_resume(struct device *dev)
if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
hda_display_power(true);
- haswell_restore_bclk(chip);
+ haswell_set_bclk(chip);
}
/* Read STATESTS before controller reset */
@@ -3793,6 +3775,10 @@ static int azx_first_init(struct azx *chip)
/* initialize chip */
azx_init_pci(chip);
+
+ if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
+ haswell_set_bclk(chip);
+
azx_init_chip(chip, (probe_only[dev] & 2) == 0);
/* codec detection */
--
1.9.1