> From: Jacob Pan <jacob.jun.pan@xxxxxxxxxxxxxxx>
> Sent: Friday, February 10, 2023 5:29 AM
>
> On platforms that do not support IOMMU Extended capability bit 0
> Page-walk Coherency, CPU caches are not snooped when IOMMU is
> accessing
> any translation structures. IOMMU access goes only directly to
> memory. Intel IOMMU code was missing a flush for the PASID table
> directory that resulted in the unrecoverable fault as shown below.
>
> This patch adds clflush calls whenever allocating and updating
> a PASID table directory to ensure cache coherency.
>
> On the reverse direction, there's no need to clflush the PASID directory
> pointer when we deactivate a context entry in that IOMMU hardware will
> not see the old PASID directory pointer after we clear the context entry.
> PASID directory entries are also never freed once allocated.
>
> [ 0.555386] DMAR: DRHD: handling fault status reg 3
> [ 0.555805] DMAR: [DMA Read NO_PASID] Request device [00:0d.2] fault
> addr 0x1026a4000 [fault reason 0x51] SM: Present bit in Directory Entry is
> clear
> [ 0.556348] DMAR: Dump dmar1 table entries for IOVA 0x1026a4000
> [ 0.556348] DMAR: scalable mode root entry: hi 0x0000000102448001, low
> 0x0000000101b3e001
> [ 0.556348] DMAR: context entry: hi 0x0000000000000000, low
> 0x0000000101b4d401
> [ 0.556348] DMAR: pasid dir entry: 0x0000000101b4e001
> [ 0.556348] DMAR: pasid table entry[0]: 0x0000000000000109
> [ 0.556348] DMAR: pasid table entry[1]: 0x0000000000000001
> [ 0.556348] DMAR: pasid table entry[2]: 0x0000000000000000
> [ 0.556348] DMAR: pasid table entry[3]: 0x0000000000000000
> [ 0.556348] DMAR: pasid table entry[4]: 0x0000000000000000
> [ 0.556348] DMAR: pasid table entry[5]: 0x0000000000000000
> [ 0.556348] DMAR: pasid table entry[6]: 0x0000000000000000
> [ 0.556348] DMAR: pasid table entry[7]: 0x0000000000000000
> [ 0.556348] DMAR: PTE not present at level 4
>
> Cc: <stable@xxxxxxxxxxxxxxx>
> Fixes: 0bbeb01a4faf ("iommu/vt-d: Manage scalalble mode PASID tables")
> Reported-by: Sukumar Ghorai <sukumar.ghorai@xxxxxxxxx>
> Signed-off-by: Ashok Raj <ashok.raj@xxxxxxxxx>
> Signed-off-by: Jacob Pan <jacob.jun.pan@xxxxxxxxxxxxxxx>
Reviewed-by: Kevin Tian <kevin.tian@xxxxxxxxx>
