On Fri, Aug 19, 2022 at 02:33:08AM +0200, Ben Hutchings wrote: > From: Ben Hutchings <benh@xxxxxxxxxx> > > The mitigation for PBRSB includes adding LFENCE instructions to the > RSB filling sequence. However, RSB filling is done on some older CPUs > that don't support the LFENCE instruction. > Wait; what? There are chips that enable the RSB mitigations and DONT have LFENCE ?!?
