From: Jeff Kirsher <jeffrey.t.kirsher@xxxxxxxxx> Date: Thu, 10 Jul 2014 01:47:15 -0700 > From: Todd Fujinaka <todd.fujinaka@xxxxxxxxx> > > On some devices, the internal PLL circuit occasionally provides the > wrong clock frequency after power up. The probability of failure is less > than one failure per 1000 power cycles. When the failure occurs, the > internal clock frequency is around 1/20 of the correct frequency. > > Cc: stable <stable@xxxxxxxxxxxxxxx> > Signed-off-by: Todd Fujinaka <todd.fujinaka@xxxxxxxxx> > Tested-by: Aaron Brown <aaron.f.brown@xxxxxxxxx> > Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@xxxxxxxxx> Applied, thanks Jeff. -- To unsubscribe from this list: send the line "unsubscribe stable" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html