On Wed, 16 Mar 2022 14:51:02 +0000,
Andre Przywara <andre.przywara@xxxxxxx> wrote:
>
> On Tue, 15 Mar 2022 16:50:32 +0000
> Marc Zyngier <maz@xxxxxxxxxx> wrote:
>
> > It turns out that our polling of RWP is totally wrong when checking
> > for it in the redistributors, as we test the *distributor* bit index,
> > whereas it is a different bit number in the RDs... Oopsie boo.
> >
> > This is embarassing. Not only because it is wrong, but also because
> > it took *8 years* to notice the blunder...
>
> Indeed, I wonder why we didn't see issues before. I guess it's either
> the UWP bit at position GICR_CTLR[31] having a similar implementation,
> or the MMIO access alone providing enough delay for the writes to
> finish.
Because we don't strictly need to wait. Most of the time, the
write will have taken place long before we can observe any effect of
it. And how often do we disable a SGI or a PPI? Almost never (the PMU
is the only one that I can think of).
> Anyway:
>
> > Just fix the damn thing.
> >
> > Fixes: 021f653791ad ("irqchip: gic-v3: Initial support for GICv3")
> > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
> > Cc: stable@xxxxxxxxxxxxxxx
>
> Reviewed-by: Andre Przywara <andre.przywara@xxxxxxx>
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
