On Tue, 15 Mar 2022 16:50:32 +0000
Marc Zyngier <maz@xxxxxxxxxx> wrote:
> It turns out that our polling of RWP is totally wrong when checking
> for it in the redistributors, as we test the *distributor* bit index,
> whereas it is a different bit number in the RDs... Oopsie boo.
>
> This is embarassing. Not only because it is wrong, but also because
> it took *8 years* to notice the blunder...
Indeed, I wonder why we didn't see issues before. I guess it's either
the UWP bit at position GICR_CTLR[31] having a similar implementation,
or the MMIO access alone providing enough delay for the writes to
finish.
Anyway:
> Just fix the damn thing.
>
> Fixes: 021f653791ad ("irqchip: gic-v3: Initial support for GICv3")
> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx
Reviewed-by: Andre Przywara <andre.przywara@xxxxxxx>
Cheers,
Andre
> ---
> drivers/irqchip/irq-gic-v3.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index 5e935d97207d..736163d36b13 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -206,11 +206,11 @@ static inline void __iomem *gic_dist_base(struct irq_data *d)
> }
> }
>
> -static void gic_do_wait_for_rwp(void __iomem *base)
> +static void gic_do_wait_for_rwp(void __iomem *base, u32 bit)
> {
> u32 count = 1000000; /* 1s! */
>
> - while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) {
> + while (readl_relaxed(base + GICD_CTLR) & bit) {
> count--;
> if (!count) {
> pr_err_ratelimited("RWP timeout, gone fishing\n");
> @@ -224,13 +224,13 @@ static void gic_do_wait_for_rwp(void __iomem *base)
> /* Wait for completion of a distributor change */
> static void gic_dist_wait_for_rwp(void)
> {
> - gic_do_wait_for_rwp(gic_data.dist_base);
> + gic_do_wait_for_rwp(gic_data.dist_base, GICD_CTLR_RWP);
> }
>
> /* Wait for completion of a redistributor change */
> static void gic_redist_wait_for_rwp(void)
> {
> - gic_do_wait_for_rwp(gic_data_rdist_rd_base());
> + gic_do_wait_for_rwp(gic_data_rdist_rd_base(), GICR_CTLR_RWP);
> }
>
> #ifdef CONFIG_ARM64
