From: Thomas Gleixner > Sent: 26 August 2020 23:08 ... > > I suspect that it is much more 'racy' than that for PCI-X interrupts. > > On the hardware side there is an interrupt disable bit, and address > > and a value. > > To raise an interrupt the hardware must write the value to the > > address. > > Really? Yep, anyone with write access to the msi-x table can get the device to write to any physical location (allowed by any IOMMU) instead of raising an interrupt. > > If the cpu needs to move an interrupt both the address and value > > need changing, but the cpu wont write the address and value using > > the same TLP, so the hardware could potentially write a value to > > the wrong address. > > Now I understand finally why msi_set_affinity() in x86 has to be so > convoluted. Updating the registers should be much the same on all architectures. I probably should have looked at what msi_set_affinity() does before deciding which order the fpga logic should read the four 32bit registers in; but they are read in increasing order - so enable bit last. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales)
