On Wed, Aug 26 2020 at 21:37, David Laight wrote: > From: Thomas Gleixner >> Sent: 26 August 2020 21:22 > ... >> Moving interrupts on x86 happens in several steps. A new vector on a >> different CPU is allocated and the relevant interrupt source is >> reprogrammed to that. But that's racy and there might be an interrupt >> already in flight to the old vector. So the old vector is preserved until >> the first interrupt arrives on the new vector and the new target CPU. Once >> that happens the old vector is cleaned up, but this cleanup still depends >> on the vector number being stored in pt_regs::orig_ax, which is now -1. > > I suspect that it is much more 'racy' than that for PCI-X interrupts. > On the hardware side there is an interrupt disable bit, and address > and a value. > To raise an interrupt the hardware must write the value to the > address. Really? > If the cpu needs to move an interrupt both the address and value > need changing, but the cpu wont write the address and value using > the same TLP, so the hardware could potentially write a value to > the wrong address. Now I understand finally why msi_set_affinity() in x86 has to be so convoluted. Thanks a lot for the enlightment! tglx