On 01/06/2014 12:07 AM, Jason Gunthorpe wrote:
On Sun, Jan 05, 2014 at 06:37:21PM +0100, Sebastian Hesselbarth wrote:
If you mean clock-gated with "powered down", the code is safe. It
enables the clock gate prior reading from the controller. Or is there
another way to power down the controller, so you cannot read from the
controller registers?
There is a clock gate and a power down on kirkwood at least, Linux has
no code for controlling the powerdown
Does that power down really disable reading from PCIe controller
registers or is it just PHY power down?
In any event, I think processing a disabled DT node is not great..
Yeah, but you see another way to get the PCIe controller registers
instead? Or any other common id register to read? IMHO PCIe ids are
the best we can find here and Gregory found the first IP that really
depends on the SoC revision..
Sebastian
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