Hi Stephen,
Le jeu. 18 avril 2019 à 1:48, Stephen Boyd <sboyd@xxxxxxxxxx> a écrit
:
Quoting Paul Cercueil (2019-04-17 04:24:20)
The pixel clock is directly connected to the output of the PLL, and
not
to the /2 divider.
Cc: stable@xxxxxxxxxxxxxxx
Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
---
Is this breaking something in 5.1-rc series? Or just found by
inspection? I'm trying to understand the priority of this patch.
I verified it with the hardware. It fixes a bug that has been present
since the introduction of this driver.
However until now nothing uses this particular clock so it can go to
5.2.
-Paul
