The pixel clock is directly connected to the output of the PLL, and not
to the /2 divider.
Cc: stable@xxxxxxxxxxxxxxx
Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")
Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
---
drivers/clk/ingenic/jz4725b-cgu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
index 8901ea0295b7..76793b3d2ef8 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -102,7 +102,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
[JZ4725B_CLK_LCD] = {
"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
- .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
+ .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
.gate = { CGU_REG_CLKGR, 9 },
},
--
2.21.0.593.g511ec345e18
