Re: [PATCH v4] mtd: spi-nor: intel-spi: Avoid crossing 4K address boundary on read/write

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On Wed, Mar 20, 2019 at 06:49:19AM +0000, Tudor.Ambarus@xxxxxxxxxxxxx wrote:
> Mika,
> 
> Would you please add your Acked-by again? It's dropped in v4.

Sure.

> Looks good for me, below is my R-b.
> 
> Thanks!
> 
> On 03/19/2019 07:18 PM, Sverdlin, Alexander (Nokia - DE/Ulm) wrote:
> > External E-Mail
> > 
> > 
> > From: Alexander Sverdlin <alexander.sverdlin@xxxxxxxxx>
> > 
> > It was observed that reads crossing 4K address boundary are failing.
> > 
> > This limitation is mentioned in Intel documents:
> > 
> > Intel(R) 9 Series Chipset Family Platform Controller Hub (PCH) Datasheet:
> > 
> > "5.26.3 Flash Access
> > Program Register Access:
> > * Program Register Accesses are not allowed to cross a 4 KB boundary..."
> > 
> > Enhanced Serial Peripheral Interface (eSPI)
> > Interface Base Specification (for Client and Server Platforms):
> > 
> > "5.1.4 Address
> > For other memory transactions, the address may start or end at any byte
> > boundary. However, the address and payload length combination must not
> > cross the naturally aligned address boundary of the corresponding Maximum
> > Payload Size. It must not cross a 4 KB address boundary."
> > 
> > Avoid this by splitting an operation crossing the boundary into two
> > operations.
> > 
> > Cc: stable@xxxxxxxxxxxxxxx
> > Reported-by: Romain Porte <romain.porte@xxxxxxxxx>
> > Tested-by: Pascal Fabreges <pascal.fabreges@xxxxxxxxx>
> > Signed-off-by: Alexander Sverdlin <alexander.sverdlin@xxxxxxxxx>
> 
> Reviewed-by: Tudor Ambarus <tudor.ambarus@xxxxxxxxxxxxx>

Acked-by: Mika Westerberg <mika.westerberg@xxxxxxxxxxxxxxx>



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