Boris Brezillon <boris.brezillon@xxxxxxxxxxxxxxxxxx> writes:
> bcm2835_pll_divider_off() is resetting the divider field in the A2W reg
> to zero when disabling the clock.
>
> Make sure we preserve this value by reading the previous a2w_reg value
> first and ORing the result with A2W_PLL_CHANNEL_DISABLE.
>
> Signed-off-by: Boris Brezillon <boris.brezillon@xxxxxxxxxxxxxxxxxx>
> Fixes: 41691b8862e2 ("clk: bcm2835: Add support for programming the audio domain clocks")
> Cc: <stable@xxxxxxxxxxxxxxx>
Reviewed-by: Eric Anholt <eric@xxxxxxxxxx>
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