Patch "arm64: dts: rockchip: fix pd_tcpc0 and pd_tcpc1 node position on rk3399" has been added to the 5.4-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    arm64: dts: rockchip: fix pd_tcpc0 and pd_tcpc1 node position on rk3399

to the 5.4-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-dts-rockchip-fix-pd_tcpc0-and-pd_tcpc1-node-po.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 07a1f8faae564f83303ca72f387dfc0d74f48bc7
Author: Johan Jonker <jbx6244@xxxxxxxxx>
Date:   Tue Apr 28 22:30:03 2020 +0200

    arm64: dts: rockchip: fix pd_tcpc0 and pd_tcpc1 node position on rk3399
    
    [ Upstream commit 2b99e6196663199409540fb95798dba464e34343 ]
    
    The pd_tcpc0 and pd_tcpc1 nodes are currently a sub node of pd_vio.
    In the rk3399 TRM figure of the 'Power Domain Partition' and in the
    table of 'Power Domain and Voltage Domain Summary' these power domains
    are positioned directly under VD_LOGIC, so fix that in 'rk3399.dtsi'.
    
    Signed-off-by: Johan Jonker <jbx6244@xxxxxxxxx>
    Reviewed-by: Caesar Wang <wxt@xxxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20200428203003.3318-2-jbx6244@xxxxxxxxx
    Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>
    Stable-dep-of: 3699f2c43ea9 ("arm64: dts: rockchip: add hevc power domain clock to rk3328")
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index dcd989563d27..04ca346b2f28 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1057,6 +1057,16 @@ pd_sdioaudio@RK3399_PD_SDIOAUDIO {
 				clocks = <&cru HCLK_SDIO>;
 				pm_qos = <&qos_sdioaudio>;
 			};
+			pd_tcpc0@RK3399_PD_TCPD0 {
+				reg = <RK3399_PD_TCPD0>;
+				clocks = <&cru SCLK_UPHY0_TCPDCORE>,
+					 <&cru SCLK_UPHY0_TCPDPHY_REF>;
+			};
+			pd_tcpc1@RK3399_PD_TCPD1 {
+				reg = <RK3399_PD_TCPD1>;
+				clocks = <&cru SCLK_UPHY1_TCPDCORE>,
+					 <&cru SCLK_UPHY1_TCPDPHY_REF>;
+			};
 			pd_usb3@RK3399_PD_USB3 {
 				reg = <RK3399_PD_USB3>;
 				clocks = <&cru ACLK_USB3>;
@@ -1089,16 +1099,6 @@ pd_isp1@RK3399_PD_ISP1 {
 					pm_qos = <&qos_isp1_m0>,
 						 <&qos_isp1_m1>;
 				};
-				pd_tcpc0@RK3399_PD_TCPD0 {
-					reg = <RK3399_PD_TCPD0>;
-					clocks = <&cru SCLK_UPHY0_TCPDCORE>,
-						 <&cru SCLK_UPHY0_TCPDPHY_REF>;
-				};
-				pd_tcpc1@RK3399_PD_TCPD1 {
-					reg = <RK3399_PD_TCPD1>;
-					clocks = <&cru SCLK_UPHY1_TCPDCORE>,
-						 <&cru SCLK_UPHY1_TCPDPHY_REF>;
-				};
 				pd_vo@RK3399_PD_VO {
 					reg = <RK3399_PD_VO>;
 					#address-cells = <1>;