From: Akshata Jahagirdar <akshata.jahagirdar@xxxxxxxxx>
commit 2009e808bc3e0df6d4d83e2271bc25ae63a4ac05 upstream.
Add Compression Performance Improvement Changes in Xe2
v2: Rebase
v3: Rebase, updated as per latest changes on bspec,
Removed unnecessary default actions (Matt)
formatting nits (Tejas)
v4: Formatting nits, removed default set action for bit 14 (Matt)
Bspec: 72161
Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar@xxxxxxxxx>
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
Link: https://patchwork.freedesktop.org/patch/msgid/c2dd753fdc55df6a6432026f2df9c2684a0d25c1.1722607628.git.akshata.jahagirdar@xxxxxxxxx
Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
drivers/gpu/drm/xe/xe_tuning.c | 5 +++++
2 files changed, 8 insertions(+)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -368,6 +368,9 @@
#define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4)
#define XEHP_LNESPARE REG_BIT(19)
+#define L3SQCREG2 XE_REG_MCR(0xb104)
+#define COMPMEMRD256BOVRFETCHEN REG_BIT(20)
+
#define L3SQCREG3 XE_REG_MCR(0xb108)
#define COMPPWOVERFETCHEN REG_BIT(28)
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -45,6 +45,11 @@ static const struct xe_rtp_entry_sr gt_t
XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
},
+ { XE_RTP_NAME("Tuning: L2 Overfetch Compressible Only"),
+ XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),
+ XE_RTP_ACTIONS(SET(L3SQCREG2,
+ COMPMEMRD256BOVRFETCHEN))
+ },
{}
};
Patches currently in stable-queue which might be from lucas.demarchi@xxxxxxxxx are
queue-6.11/drm-xe-add-mmio-read-before-ggtt-invalidate.patch
queue-6.11/drm-i915-disable-fbc-due-to-wa_16023588340.patch
queue-6.11/drm-i915-skip-programming-fia-link-enable-bits-for-mtl.patch
queue-6.11/drm-i915-display-cache-adpative-sync-caps-to-use-it-later.patch
queue-6.11/drm-i915-display-don-t-enable-decompression-on-xe2-with-tile4.patch
queue-6.11/drm-xe-xe2-introduce-performance-changes.patch
queue-6.11/drm-xe-define-stateless_compression_ctrl-as-mcr-register.patch
queue-6.11/drm-i915-hdcp-add-encoder-check-in-hdcp2_get_capability.patch
queue-6.11/drm-i915-hdcp-add-encoder-check-in-intel_hdcp_get_capability.patch
queue-6.11/drm-xe-don-t-short-circuit-tdr-on-jobs-not-started.patch
queue-6.11/drm-xe-write-all-slices-if-its-mcr-register.patch
queue-6.11/drm-i915-move-rawclk-from-runtime-to-display-runtime-info.patch
queue-6.11/drm-xe-display-drop-unused-rawclk_freq-and-runtime_info.patch
queue-6.11/drm-xe-xe2hpg-add-wa_15016589081.patch
queue-6.11/drm-i915-display-dp-compute-as-sdp-when-vrr-is-also-enabled.patch
queue-6.11/drm-i915-pps-disable-dpls_gating-around-pps-sequence.patch
queue-6.11/drm-i915-dp-clear-vsc-sdp-during-post-ddi-disable-routine.patch
queue-6.11/drm-xe-xe2-add-performance-turning-changes.patch
queue-6.11/drm-i915-psr-prevent-panel-replay-if-crc-calculation-is-enabled.patch
queue-6.11/drm-xe-move-enable-host-l2-vram-post-mcr-init.patch
queue-6.11/drm-xe-support-nomodeset-kernel-command-line-option.patch
queue-6.11/drm-xe-xe2hpg-introduce-performance-tuning-changes-for-xe2_hpg.patch
queue-6.11/drm-i915-display-wa-for-re-initialize-dispcnlunitt1-xosc-clock.patch
