From: Shekhar Chauhan <shekhar.chauhan@xxxxxxxxx> commit ecabb5e6ce54711c28706fc794d77adb3ecd0605 upstream. Update performance tuning according to the hardware spec. Bspec: 72161 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@xxxxxxxxx> Reviewed-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@xxxxxxxxx> Reviewed-by: Akshata Jahagirdar <akshata.jahagirdar@xxxxxxxxx> Signed-off-by: Matt Roper <matthew.d.roper@xxxxxxxxx> Link: https://patchwork.freedesktop.org/patch/msgid/20240805053710.877119-1-shekhar.chauhan@xxxxxxxxx Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 4 ++++ drivers/gpu/drm/xe/xe_tuning.c | 8 +++++++- 2 files changed, 11 insertions(+), 1 deletion(-) --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -80,6 +80,9 @@ #define LE_CACHEABILITY_MASK REG_GENMASK(1, 0) #define LE_CACHEABILITY(value) REG_FIELD_PREP(LE_CACHEABILITY_MASK, value) +#define STATELESS_COMPRESSION_CTRL XE_REG(0x4148) +#define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0) + #define XE2_GAMREQSTRM_CTRL XE_REG(0x4194) #define CG_DIS_CNTLBUS REG_BIT(6) @@ -194,6 +197,7 @@ #define GSCPSMI_BASE XE_REG(0x880c) #define CCCHKNREG1 XE_REG_MCR(0x8828) +#define L3CMPCTRL REG_BIT(23) #define ENCOMPPERFFIX REG_BIT(18) /* Fuse readout registers for GT */ --- a/drivers/gpu/drm/xe/xe_tuning.c +++ b/drivers/gpu/drm/xe/xe_tuning.c @@ -39,7 +39,8 @@ static const struct xe_rtp_entry_sr gt_t }, { XE_RTP_NAME("Tuning: Compression Overfetch"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), - XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX)), + XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX), + SET(CCCHKNREG1, L3CMPCTRL)) }, { XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"), XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), @@ -50,6 +51,11 @@ static const struct xe_rtp_entry_sr gt_t XE_RTP_ACTIONS(SET(L3SQCREG2, COMPMEMRD256BOVRFETCHEN)) }, + { XE_RTP_NAME("Tuning: Stateless compression control"), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)), + XE_RTP_ACTIONS(FIELD_SET(STATELESS_COMPRESSION_CTRL, UNIFIED_COMPRESSION_FORMAT, + REG_FIELD_PREP(UNIFIED_COMPRESSION_FORMAT, 0))) + }, {} }; Patches currently in stable-queue which might be from lucas.demarchi@xxxxxxxxx are queue-6.11/drm-xe-add-mmio-read-before-ggtt-invalidate.patch queue-6.11/drm-i915-disable-fbc-due-to-wa_16023588340.patch queue-6.11/drm-i915-skip-programming-fia-link-enable-bits-for-mtl.patch queue-6.11/drm-i915-display-cache-adpative-sync-caps-to-use-it-later.patch queue-6.11/drm-i915-display-don-t-enable-decompression-on-xe2-with-tile4.patch queue-6.11/drm-xe-xe2-introduce-performance-changes.patch queue-6.11/drm-xe-define-stateless_compression_ctrl-as-mcr-register.patch queue-6.11/drm-i915-hdcp-add-encoder-check-in-hdcp2_get_capability.patch queue-6.11/drm-i915-hdcp-add-encoder-check-in-intel_hdcp_get_capability.patch queue-6.11/drm-xe-don-t-short-circuit-tdr-on-jobs-not-started.patch queue-6.11/drm-xe-write-all-slices-if-its-mcr-register.patch queue-6.11/drm-i915-move-rawclk-from-runtime-to-display-runtime-info.patch queue-6.11/drm-xe-display-drop-unused-rawclk_freq-and-runtime_info.patch queue-6.11/drm-xe-xe2hpg-add-wa_15016589081.patch queue-6.11/drm-i915-display-dp-compute-as-sdp-when-vrr-is-also-enabled.patch queue-6.11/drm-i915-pps-disable-dpls_gating-around-pps-sequence.patch queue-6.11/drm-i915-dp-clear-vsc-sdp-during-post-ddi-disable-routine.patch queue-6.11/drm-xe-xe2-add-performance-turning-changes.patch queue-6.11/drm-i915-psr-prevent-panel-replay-if-crc-calculation-is-enabled.patch queue-6.11/drm-xe-move-enable-host-l2-vram-post-mcr-init.patch queue-6.11/drm-xe-support-nomodeset-kernel-command-line-option.patch queue-6.11/drm-xe-xe2hpg-introduce-performance-tuning-changes-for-xe2_hpg.patch queue-6.11/drm-i915-display-wa-for-re-initialize-dispcnlunitt1-xosc-clock.patch
