Patch "irqchip/renesas-rzg2l: Flush posted write in irq_eoi()" has been added to the 6.6-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    irqchip/renesas-rzg2l: Flush posted write in irq_eoi()

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     irqchip-renesas-rzg2l-flush-posted-write-in-irq_eoi.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 0a5c84a3d45934556ca1106a6baef7ed6af9a1e0
Author: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Date:   Tue Mar 5 18:39:18 2024 +0000

    irqchip/renesas-rzg2l: Flush posted write in irq_eoi()
    
    [ Upstream commit 9eec61df55c51415409c7cc47e9a1c8de94a0522 ]
    
    The irq_eoi() callback of the RZ/G2L interrupt chip clears the relevant
    interrupt cause bit in the TSCR register by writing to it.
    
    This write is not sufficient because the write is posted and therefore not
    guaranteed to immediately clear the bit. Due to that delay the CPU can
    raise the just handled interrupt again.
    
    Prevent this by reading the register back which causes the posted write to
    be flushed to the hardware before the read completes.
    
    Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver")
    Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
    Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index 8e0b15c7fe7f1..7ea646e3e287f 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -81,8 +81,14 @@ static void rzg2l_irq_eoi(struct irq_data *d)
 	 * ISCR can only be cleared if the type is falling-edge, rising-edge or
 	 * falling/rising-edge.
 	 */
-	if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq)))
+	if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) {
 		writel_relaxed(iscr & ~bit, priv->base + ISCR);
+		/*
+		 * Enforce that the posted write is flushed to prevent that the
+		 * just handled interrupt is raised again.
+		 */
+		readl_relaxed(priv->base + ISCR);
+	}
 }
 
 static void rzg2l_tint_eoi(struct irq_data *d)
@@ -93,8 +99,14 @@ static void rzg2l_tint_eoi(struct irq_data *d)
 	u32 reg;
 
 	reg = readl_relaxed(priv->base + TSCR);
-	if (reg & bit)
+	if (reg & bit) {
 		writel_relaxed(reg & ~bit, priv->base + TSCR);
+		/*
+		 * Enforce that the posted write is flushed to prevent that the
+		 * just handled interrupt is raised again.
+		 */
+		readl_relaxed(priv->base + TSCR);
+	}
 }
 
 static void rzg2l_irqc_eoi(struct irq_data *d)