Patch "clk: qcom: dispcc-sm8550: Use the correct PLL configuration function" has been added to the 6.7-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: qcom: dispcc-sm8550: Use the correct PLL configuration function

to the 6.7-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-qcom-dispcc-sm8550-use-the-correct-pll-configura.patch
and it can be found in the queue-6.7 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 61fdb3f2b316c70bc2523d3ecfca5f0142381ca8
Author: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Date:   Mon Dec 18 17:02:10 2023 +0100

    clk: qcom: dispcc-sm8550: Use the correct PLL configuration function
    
    [ Upstream commit c559bcb92564cbaedd43c749cf9b6fbb3d53ad5e ]
    
    To ensure that all fields (particularly CAL_L and CAL_L_RINGOSC) are
    filled properly, use the correct prepare function for OLE PLLs.
    
    Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver")
    Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20231218-topic-8550_fixes-v1-9-ce1272d77540@xxxxxxxxxx
    Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c
index 0b8f0904b339..f96d8b81fd9a 100644
--- a/drivers/clk/qcom/dispcc-sm8550.c
+++ b/drivers/clk/qcom/dispcc-sm8550.c
@@ -1774,8 +1774,8 @@ static int disp_cc_sm8550_probe(struct platform_device *pdev)
 		goto err_put_rpm;
 	}
 
-	clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
-	clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
+	clk_lucid_ole_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
+	clk_lucid_ole_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
 
 	/* Enable clock gating for MDP clocks */
 	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);




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