Patch "drm/amdgpu: Increase IH soft ring size for GFX v9.4.3 dGPU" has been added to the 6.5-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/amdgpu: Increase IH soft ring size for GFX v9.4.3 dGPU

to the 6.5-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amdgpu-increase-ih-soft-ring-size-for-gfx-v9.4.3.patch
and it can be found in the queue-6.5 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit f3ff7f4ff1b93064b3d8d71d8dc32f5cfdc87d51
Author: Philip Yang <Philip.Yang@xxxxxxx>
Date:   Fri Sep 15 15:13:48 2023 -0400

    drm/amdgpu: Increase IH soft ring size for GFX v9.4.3 dGPU
    
    [ Upstream commit bcfb9cee61207b80f37663ffa08c135657a27ad5 ]
    
    On GFX v9.4.3 dGPU, applications have random timeout failure when XNACK
    on, dmesg log has "amdgpu: IH soft ring buffer overflow 0x900, 0x900",
    because dGPU mode has 272 cam entries. After increasing IH soft ring
    to 512 entries, no more IH soft ring overflow message and application
    passed.
    
    Fixes: bf80d34b6c58 ("drm/amdgpu: Increase soft IH ring size")
    Signed-off-by: Philip Yang <Philip.Yang@xxxxxxx>
    Reviewed-by: Christian König <christian.koenig@xxxxxxx>
    Reviewed-by: Felix Kuehling <Felix.Kuehling@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index 6c6184f0dbc17..508f02eb0cf8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -28,7 +28,7 @@
 #define AMDGPU_IH_MAX_NUM_IVS	32
 
 #define IH_RING_SIZE	(256 * 1024)
-#define IH_SW_RING_SIZE	(8 * 1024)	/* enough for 256 CAM entries */
+#define IH_SW_RING_SIZE	(16 * 1024)	/* enough for 512 CAM entries */
 
 struct amdgpu_device;
 struct amdgpu_iv_entry;



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