From: James Morse <james.morse@xxxxxxx>
arm64_update_smccc_conduit() is an alternative callback that patches
HVC/SMC. Currently the only user is SSBD. To use this for Spectre-BHB,
it needs to be moved out of the SSBD #ifdef region.
Signed-off-by: James Morse <james.morse@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/arm64/kernel/cpu_errata.c | 44 ++++++++++++++++++++---------------------
1 file changed, 22 insertions(+), 22 deletions(-)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -204,6 +204,28 @@ enable_smccc_arch_workaround_1(const str
}
#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
+void __init arm64_update_smccc_conduit(struct alt_instr *alt,
+ __le32 *origptr, __le32 *updptr,
+ int nr_inst)
+{
+ u32 insn;
+
+ BUG_ON(nr_inst != 1);
+
+ switch (psci_ops.conduit) {
+ case PSCI_CONDUIT_HVC:
+ insn = aarch64_insn_get_hvc_value();
+ break;
+ case PSCI_CONDUIT_SMC:
+ insn = aarch64_insn_get_smc_value();
+ break;
+ default:
+ return;
+ }
+
+ *updptr = cpu_to_le32(insn);
+}
+
#ifdef CONFIG_ARM64_SSBD
DEFINE_PER_CPU_READ_MOSTLY(u64, arm64_ssbd_callback_required);
@@ -239,28 +261,6 @@ static int __init ssbd_cfg(char *buf)
}
early_param("ssbd", ssbd_cfg);
-void __init arm64_update_smccc_conduit(struct alt_instr *alt,
- __le32 *origptr, __le32 *updptr,
- int nr_inst)
-{
- u32 insn;
-
- BUG_ON(nr_inst != 1);
-
- switch (psci_ops.conduit) {
- case PSCI_CONDUIT_HVC:
- insn = aarch64_insn_get_hvc_value();
- break;
- case PSCI_CONDUIT_SMC:
- insn = aarch64_insn_get_smc_value();
- break;
- default:
- return;
- }
-
- *updptr = cpu_to_le32(insn);
-}
-
void __init arm64_enable_wa2_handling(struct alt_instr *alt,
__le32 *origptr, __le32 *updptr,
int nr_inst)
Patches currently in stable-queue which might be from james.morse@xxxxxxx are
queue-4.9/clocksource-drivers-arm_arch_timer-remove-fsl-a008585-parameter.patch
queue-4.9/arm64-capabilities-clean-up-midr-range-helpers.patch
queue-4.9/arm64-entry-add-macro-for-reading-symbol-addresses-from-the-trampoline.patch
queue-4.9/arm64-use-the-clearbhb-instruction-in-mitigations.patch
queue-4.9/arm64-add-percpu-vectors-for-el1.patch
queue-4.9/arm64-arch_timer-add-workaround-for-arm-erratum-1188873.patch
queue-4.9/arm64-capabilities-add-support-for-checks-based-on-a-list-of-midrs.patch
queue-4.9/arm64-arch_timer-add-infrastructure-for-multiple-erratum-detection-methods.patch
queue-4.9/arm64-entry-free-up-another-register-on-kpti-s-tramp_exit-path.patch
queue-4.9/arm64-entry-don-t-assume-tramp_vectors-is-the-start-of-the-vectors.patch
queue-4.9/arm64-entry-make-the-trampoline-cleanup-optional.patch
queue-4.9/arm64-add-silicon-errata.txt-entry-for-arm-erratum-1188873.patch
queue-4.9/clocksource-drivers-arm_arch_timer-introduce-generic-errata-handling-infrastructure.patch
queue-4.9/kvm-arm64-add-templates-for-bhb-mitigation-sequences.patch
queue-4.9/arm64-entry-add-non-kpti-__bp_harden_el1_vectors-for-mitigations.patch
queue-4.9/arm64-add-id_aa64isar2_el1-sys-register.patch
queue-4.9/kvm-arm64-allow-smccc_arch_workaround_3-to-be-discovered-and-migrated.patch
queue-4.9/arm64-capabilities-update-prototype-for-enable-call-back.patch
queue-4.9/arm64-add-neoverse-n2-cortex-a710-cpu-part-definition.patch
queue-4.9/arm64-add-midr-encoding-for-arm-cortex-a55-and-cortex-a35.patch
queue-4.9/arm64-capabilities-move-errata-processing-code.patch
queue-4.9/arm64-arch_timer-add-erratum-handler-for-cpu-specific-capability.patch
queue-4.9/arm64-errata-provide-macro-for-major-and-minor-cpu-revisions.patch
queue-4.9/arm64-arch_timer-avoid-unused-function-warning.patch
queue-4.9/arm64-capabilities-move-errata-work-around-check-on-boot-cpu.patch
queue-4.9/arm64-add-helpers-for-checking-cpu-midr-against-a-range.patch
queue-4.9/arm64-entry-move-trampoline-macros-out-of-ifdef-d-section.patch
queue-4.9/arm64-entry-allow-tramp_alias-to-access-symbols-after-the-4k-boundary.patch
queue-4.9/arm64-add-part-number-for-arm-cortex-a77.patch
queue-4.9/arm64-capabilities-add-flags-to-handle-the-conflicts-on-late-cpu.patch
queue-4.9/arm64-entry-move-the-trampoline-data-page-before-the-text-page.patch
queue-4.9/arm64-entry.s-add-ventry-overflow-sanity-checks.patch
queue-4.9/arm64-add-part-number-for-neoverse-n1.patch
queue-4.9/arm64-entry-add-vectors-that-have-the-bhb-mitigation-sequences.patch
queue-4.9/arm64-make-arm64_erratum_1188873-depend-on-compat.patch
queue-4.9/arm64-mitigate-spectre-style-branch-history-side-channels.patch
queue-4.9/arm64-move-arm64_update_smccc_conduit-out-of-ssbd-ifdef.patch
queue-4.9/arm64-entry-allow-the-trampoline-text-to-occupy-multiple-pages.patch
queue-4.9/arm64-add-cortex-x2-cpu-part-definition.patch
queue-4.9/arm64-add-helper-to-decode-register-from-instruction.patch
queue-4.9/arm64-capabilities-prepare-for-fine-grained-capabilities.patch
queue-4.9/arm64-remove-useless-uao-ipi-and-describe-how-this-gets-enabled.patch
queue-4.9/arm64-entry-make-the-kpti-trampoline-s-kpti-sequence-optional.patch
