From: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
commit 8c2dcbd2c4443bad0b4242fb62baa47b260b8f79 upstream.
Add a helper to extract the register field from a given
instruction.
Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
Cc: Will Deacon <will.deacon@xxxxxxx>
Cc: Mark Rutland <mark.rutland@xxxxxxx>
Reviewed-by: Catalin Marinas <catalin.marinas@xxxxxxx>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
Signed-off-by: Will Deacon <will.deacon@xxxxxxx>
Signed-off-by: James Morse <james.morse@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/arm64/include/asm/insn.h | 2 ++
arch/arm64/kernel/insn.c | 29 +++++++++++++++++++++++++++++
2 files changed, 31 insertions(+)
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -332,6 +332,8 @@ bool aarch64_insn_is_branch(u32 insn);
u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
u32 insn, u64 imm);
+u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
+ u32 insn);
u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
enum aarch64_insn_branch_type type);
u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -418,6 +418,35 @@ u32 __kprobes aarch64_insn_encode_immedi
return insn;
}
+u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
+ u32 insn)
+{
+ int shift;
+
+ switch (type) {
+ case AARCH64_INSN_REGTYPE_RT:
+ case AARCH64_INSN_REGTYPE_RD:
+ shift = 0;
+ break;
+ case AARCH64_INSN_REGTYPE_RN:
+ shift = 5;
+ break;
+ case AARCH64_INSN_REGTYPE_RT2:
+ case AARCH64_INSN_REGTYPE_RA:
+ shift = 10;
+ break;
+ case AARCH64_INSN_REGTYPE_RM:
+ shift = 16;
+ break;
+ default:
+ pr_err("%s: unknown register type encoding %d\n", __func__,
+ type);
+ return 0;
+ }
+
+ return (insn >> shift) & GENMASK(4, 0);
+}
+
static u32 aarch64_insn_encode_register(enum aarch64_insn_register_type type,
u32 insn,
enum aarch64_insn_register reg)
Patches currently in stable-queue which might be from james.morse@xxxxxxx are
queue-4.9/clocksource-drivers-arm_arch_timer-remove-fsl-a008585-parameter.patch
queue-4.9/arm64-capabilities-clean-up-midr-range-helpers.patch
queue-4.9/arm64-entry-add-macro-for-reading-symbol-addresses-from-the-trampoline.patch
queue-4.9/arm64-use-the-clearbhb-instruction-in-mitigations.patch
queue-4.9/arm64-add-percpu-vectors-for-el1.patch
queue-4.9/arm64-arch_timer-add-workaround-for-arm-erratum-1188873.patch
queue-4.9/arm64-capabilities-add-support-for-checks-based-on-a-list-of-midrs.patch
queue-4.9/arm64-arch_timer-add-infrastructure-for-multiple-erratum-detection-methods.patch
queue-4.9/arm64-entry-free-up-another-register-on-kpti-s-tramp_exit-path.patch
queue-4.9/arm64-entry-don-t-assume-tramp_vectors-is-the-start-of-the-vectors.patch
queue-4.9/arm64-entry-make-the-trampoline-cleanup-optional.patch
queue-4.9/arm64-add-silicon-errata.txt-entry-for-arm-erratum-1188873.patch
queue-4.9/clocksource-drivers-arm_arch_timer-introduce-generic-errata-handling-infrastructure.patch
queue-4.9/kvm-arm64-add-templates-for-bhb-mitigation-sequences.patch
queue-4.9/arm64-entry-add-non-kpti-__bp_harden_el1_vectors-for-mitigations.patch
queue-4.9/arm64-add-id_aa64isar2_el1-sys-register.patch
queue-4.9/kvm-arm64-allow-smccc_arch_workaround_3-to-be-discovered-and-migrated.patch
queue-4.9/arm64-capabilities-update-prototype-for-enable-call-back.patch
queue-4.9/arm64-add-neoverse-n2-cortex-a710-cpu-part-definition.patch
queue-4.9/arm64-add-midr-encoding-for-arm-cortex-a55-and-cortex-a35.patch
queue-4.9/arm64-capabilities-move-errata-processing-code.patch
queue-4.9/arm64-arch_timer-add-erratum-handler-for-cpu-specific-capability.patch
queue-4.9/arm64-errata-provide-macro-for-major-and-minor-cpu-revisions.patch
queue-4.9/arm64-arch_timer-avoid-unused-function-warning.patch
queue-4.9/arm64-capabilities-move-errata-work-around-check-on-boot-cpu.patch
queue-4.9/arm64-add-helpers-for-checking-cpu-midr-against-a-range.patch
queue-4.9/arm64-entry-move-trampoline-macros-out-of-ifdef-d-section.patch
queue-4.9/arm64-entry-allow-tramp_alias-to-access-symbols-after-the-4k-boundary.patch
queue-4.9/arm64-add-part-number-for-arm-cortex-a77.patch
queue-4.9/arm64-capabilities-add-flags-to-handle-the-conflicts-on-late-cpu.patch
queue-4.9/arm64-entry-move-the-trampoline-data-page-before-the-text-page.patch
queue-4.9/arm64-entry.s-add-ventry-overflow-sanity-checks.patch
queue-4.9/arm64-add-part-number-for-neoverse-n1.patch
queue-4.9/arm64-entry-add-vectors-that-have-the-bhb-mitigation-sequences.patch
queue-4.9/arm64-make-arm64_erratum_1188873-depend-on-compat.patch
queue-4.9/arm64-mitigate-spectre-style-branch-history-side-channels.patch
queue-4.9/arm64-move-arm64_update_smccc_conduit-out-of-ssbd-ifdef.patch
queue-4.9/arm64-entry-allow-the-trampoline-text-to-occupy-multiple-pages.patch
queue-4.9/arm64-add-cortex-x2-cpu-part-definition.patch
queue-4.9/arm64-add-helper-to-decode-register-from-instruction.patch
queue-4.9/arm64-capabilities-prepare-for-fine-grained-capabilities.patch
queue-4.9/arm64-remove-useless-uao-ipi-and-describe-how-this-gets-enabled.patch
queue-4.9/arm64-entry-make-the-kpti-trampoline-s-kpti-sequence-optional.patch
