From: Marc Zyngier <marc.zyngier@xxxxxxx>
commit 0064030c6fd4ca6cfab42de037b2a89445beeead upstream.
Should we ever have a workaround for an erratum that is detected using
a capability and affecting a particular CPU, it'd be nice to have
a way to probe them directly.
Acked-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
Signed-off-by: Marc Zyngier <marc.zyngier@xxxxxxx>
Signed-off-by: James Morse <james.morse@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/arm64/include/asm/arch_timer.h | 1 +
drivers/clocksource/arm_arch_timer.c | 28 ++++++++++++++++++++++++----
2 files changed, 25 insertions(+), 4 deletions(-)
--- a/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@ -39,6 +39,7 @@ extern struct static_key_false arch_time
enum arch_timer_erratum_match_type {
ate_match_dt,
+ ate_match_local_cap_id,
};
struct arch_timer_erratum_workaround {
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -162,6 +162,13 @@ bool arch_timer_check_dt_erratum(const s
return of_property_read_bool(np, wa->id);
}
+static
+bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
+ const void *arg)
+{
+ return this_cpu_has_cap((uintptr_t)wa->id);
+}
+
static const struct arch_timer_erratum_workaround *
arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
ate_match_fn_t match_fn,
@@ -192,14 +199,16 @@ static void arch_timer_check_ool_workaro
{
const struct arch_timer_erratum_workaround *wa;
ate_match_fn_t match_fn = NULL;
-
- if (static_branch_unlikely(&arch_timer_read_ool_enabled))
- return;
+ bool local = false;
switch (type) {
case ate_match_dt:
match_fn = arch_timer_check_dt_erratum;
break;
+ case ate_match_local_cap_id:
+ match_fn = arch_timer_check_local_cap_erratum;
+ local = true;
+ break;
default:
WARN_ON(1);
return;
@@ -209,8 +218,17 @@ static void arch_timer_check_ool_workaro
if (!wa)
return;
+ if (needs_unstable_timer_counter_workaround()) {
+ if (wa != timer_unstable_counter_workaround)
+ pr_warn("Can't enable workaround for %s (clashes with %s\n)",
+ wa->desc,
+ timer_unstable_counter_workaround->desc);
+ return;
+ }
+
arch_timer_enable_workaround(wa);
- pr_info("Enabling global workaround for %s\n", wa->desc);
+ pr_info("Enabling %s workaround for %s\n",
+ local ? "local" : "global", wa->desc);
}
#else
@@ -470,6 +488,8 @@ static void __arch_timer_setup(unsigned
BUG();
}
+ arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
+
erratum_workaround_set_sne(clk);
} else {
clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
Patches currently in stable-queue which might be from james.morse@xxxxxxx are
queue-4.9/clocksource-drivers-arm_arch_timer-remove-fsl-a008585-parameter.patch
queue-4.9/arm64-capabilities-clean-up-midr-range-helpers.patch
queue-4.9/arm64-entry-add-macro-for-reading-symbol-addresses-from-the-trampoline.patch
queue-4.9/arm64-use-the-clearbhb-instruction-in-mitigations.patch
queue-4.9/arm64-add-percpu-vectors-for-el1.patch
queue-4.9/arm64-arch_timer-add-workaround-for-arm-erratum-1188873.patch
queue-4.9/arm64-capabilities-add-support-for-checks-based-on-a-list-of-midrs.patch
queue-4.9/arm64-arch_timer-add-infrastructure-for-multiple-erratum-detection-methods.patch
queue-4.9/arm64-entry-free-up-another-register-on-kpti-s-tramp_exit-path.patch
queue-4.9/arm64-entry-don-t-assume-tramp_vectors-is-the-start-of-the-vectors.patch
queue-4.9/arm64-entry-make-the-trampoline-cleanup-optional.patch
queue-4.9/arm64-add-silicon-errata.txt-entry-for-arm-erratum-1188873.patch
queue-4.9/clocksource-drivers-arm_arch_timer-introduce-generic-errata-handling-infrastructure.patch
queue-4.9/kvm-arm64-add-templates-for-bhb-mitigation-sequences.patch
queue-4.9/arm64-entry-add-non-kpti-__bp_harden_el1_vectors-for-mitigations.patch
queue-4.9/arm64-add-id_aa64isar2_el1-sys-register.patch
queue-4.9/kvm-arm64-allow-smccc_arch_workaround_3-to-be-discovered-and-migrated.patch
queue-4.9/arm64-capabilities-update-prototype-for-enable-call-back.patch
queue-4.9/arm64-add-neoverse-n2-cortex-a710-cpu-part-definition.patch
queue-4.9/arm64-add-midr-encoding-for-arm-cortex-a55-and-cortex-a35.patch
queue-4.9/arm64-capabilities-move-errata-processing-code.patch
queue-4.9/arm64-arch_timer-add-erratum-handler-for-cpu-specific-capability.patch
queue-4.9/arm64-errata-provide-macro-for-major-and-minor-cpu-revisions.patch
queue-4.9/arm64-arch_timer-avoid-unused-function-warning.patch
queue-4.9/arm64-capabilities-move-errata-work-around-check-on-boot-cpu.patch
queue-4.9/arm64-add-helpers-for-checking-cpu-midr-against-a-range.patch
queue-4.9/arm64-entry-move-trampoline-macros-out-of-ifdef-d-section.patch
queue-4.9/arm64-entry-allow-tramp_alias-to-access-symbols-after-the-4k-boundary.patch
queue-4.9/arm64-add-part-number-for-arm-cortex-a77.patch
queue-4.9/arm64-capabilities-add-flags-to-handle-the-conflicts-on-late-cpu.patch
queue-4.9/arm64-entry-move-the-trampoline-data-page-before-the-text-page.patch
queue-4.9/arm64-entry.s-add-ventry-overflow-sanity-checks.patch
queue-4.9/arm64-add-part-number-for-neoverse-n1.patch
queue-4.9/arm64-entry-add-vectors-that-have-the-bhb-mitigation-sequences.patch
queue-4.9/arm64-make-arm64_erratum_1188873-depend-on-compat.patch
queue-4.9/arm64-mitigate-spectre-style-branch-history-side-channels.patch
queue-4.9/arm64-move-arm64_update_smccc_conduit-out-of-ssbd-ifdef.patch
queue-4.9/arm64-entry-allow-the-trampoline-text-to-occupy-multiple-pages.patch
queue-4.9/arm64-add-cortex-x2-cpu-part-definition.patch
queue-4.9/arm64-add-helper-to-decode-register-from-instruction.patch
queue-4.9/arm64-capabilities-prepare-for-fine-grained-capabilities.patch
queue-4.9/arm64-remove-useless-uao-ipi-and-describe-how-this-gets-enabled.patch
queue-4.9/arm64-entry-make-the-kpti-trampoline-s-kpti-sequence-optional.patch
