From: Rob Herring <robh@xxxxxxxxxx> commit 8a6b88e66233f5f1779b0a1342aa9dc030dddcd5 upstream. Add the MIDR part number info for the Arm Cortex-A77. Signed-off-by: Rob Herring <robh@xxxxxxxxxx> Acked-by: Catalin Marinas <catalin.marinas@xxxxxxx> Cc: Catalin Marinas <catalin.marinas@xxxxxxx> Cc: Will Deacon <will@xxxxxxxxxx> Link: https://lore.kernel.org/r/20201028182839.166037-1-robh@xxxxxxxxxx Signed-off-by: Will Deacon <will@xxxxxxxxxx> Signed-off-by: James Morse <james.morse@xxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -81,6 +81,7 @@ #define ARM_CPU_PART_CORTEX_A55 0xD05 #define ARM_CPU_PART_CORTEX_A76 0xD0B #define ARM_CPU_PART_NEOVERSE_N1 0xD0C +#define ARM_CPU_PART_CORTEX_A77 0xD0D #define APM_CPU_PART_POTENZA 0x000 @@ -109,6 +110,7 @@ #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) +#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) Patches currently in stable-queue which might be from james.morse@xxxxxxx are queue-4.19/arm64-entry-add-macro-for-reading-symbol-addresses-from-the-trampoline.patch queue-4.19/arm64-use-the-clearbhb-instruction-in-mitigations.patch queue-4.19/arm64-add-percpu-vectors-for-el1.patch queue-4.19/arm64-entry-free-up-another-register-on-kpti-s-tramp_exit-path.patch queue-4.19/arm64-entry-don-t-assume-tramp_vectors-is-the-start-of-the-vectors.patch queue-4.19/arm64-entry-make-the-trampoline-cleanup-optional.patch queue-4.19/kvm-arm64-add-templates-for-bhb-mitigation-sequences.patch queue-4.19/arm64-entry-add-non-kpti-__bp_harden_el1_vectors-for-mitigations.patch queue-4.19/arm64-add-id_aa64isar2_el1-sys-register.patch queue-4.19/kvm-arm64-allow-smccc_arch_workaround_3-to-be-discovered-and-migrated.patch queue-4.19/arm64-add-neoverse-n2-cortex-a710-cpu-part-definition.patch queue-4.19/arm64-entry-move-trampoline-macros-out-of-ifdef-d-section.patch queue-4.19/arm64-entry-allow-tramp_alias-to-access-symbols-after-the-4k-boundary.patch queue-4.19/arm64-add-part-number-for-arm-cortex-a77.patch queue-4.19/arm64-entry-move-the-trampoline-data-page-before-the-text-page.patch queue-4.19/arm64-entry.s-add-ventry-overflow-sanity-checks.patch queue-4.19/arm64-entry-add-vectors-that-have-the-bhb-mitigation-sequences.patch queue-4.19/arm64-mitigate-spectre-style-branch-history-side-channels.patch queue-4.19/arm64-entry-allow-the-trampoline-text-to-occupy-multiple-pages.patch queue-4.19/arm64-proton-pack-report-spectre-bhb-vulnerabilities-as-part-of-spectre-v2.patch queue-4.19/arm64-add-cortex-x2-cpu-part-definition.patch queue-4.19/arm64-entry-make-the-kpti-trampoline-s-kpti-sequence-optional.patch
