This is a note to let you know that I've just added the patch titled
arm64: dts: ti: k3-j721e: Fix the L2 cache sets
to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-dts-ti-k3-j721e-fix-the-l2-cache-sets.patch
and it can be found in the queue-5.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit 1ca75b78e81b5473c4ca841e3c3250ef294d046d
Author: Nishanth Menon <nm@xxxxxx>
Date: Fri Nov 12 22:36:39 2021 -0600
arm64: dts: ti: k3-j721e: Fix the L2 cache sets
[ Upstream commit e9ba3a5bc6fdc2c796c69fdaf5ed6c9957cf9f9d ]
A72's L2 cache[1] on J721e[2] is 1MB. A72's L2 is fixed line length of
64 bytes and 16-way set-associative cache structure.
1MB of L2 / 64 (line length) = 16384 ways
16384 ways / 16 = 1024 sets
Fix the l2 cache-sets.
[1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
[2] http://www.ti.com/lit/pdf/spruil1
Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC")
Reported-by: Peng Fan <peng.fan@xxxxxxx>
Signed-off-by: Nishanth Menon <nm@xxxxxx>
Reviewed-by: Pratyush Yadav <p.yadav@xxxxxx>
Signed-off-by: Vignesh Raghavendra <vigneshr@xxxxxx>
Link: https://lore.kernel.org/r/20211113043639.4413-1-nm@xxxxxx
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index f4d8f3b37d5bb..5a6e74636d6fc 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -84,7 +84,7 @@ L2_0: l2-cache0 {
cache-level = <2>;
cache-size = <0x100000>;
cache-line-size = <64>;
- cache-sets = <2048>;
+ cache-sets = <1024>;
next-level-cache = <&msmc_l3>;
};
