This is a note to let you know that I've just added the patch titled
PCI: Add PCI_EXP_LNKCTL2_TLS* macros
to the 4.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
pci-add-pci_exp_lnkctl2_tls-macros.patch
and it can be found in the queue-4.14 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From foo@baz Mon Nov 29 01:32:04 PM CET 2021
From: "Marek Behún" <kabel@xxxxxxxxxx>
Date: Wed, 24 Nov 2021 23:49:26 +0100
Subject: PCI: Add PCI_EXP_LNKCTL2_TLS* macros
To: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>, Sasha Levin <sashal@xxxxxxxxxx>
Cc: pali@xxxxxxxxxx, stable@xxxxxxxxxxxxxxx, "Frederick Lawler" <fred@xxxxxxxxxxxx>, "Bjorn Helgaas" <bhelgaas@xxxxxxxxxx>, "Marek Behún" <kabel@xxxxxxxxxx>
Message-ID: <20211124224933.24275-18-kabel@xxxxxxxxxx>
From: Frederick Lawler <fred@xxxxxxxxxxxx>
commit c80851f6ce63a6e313f8c7b4b6eb82c67aa4497b upstream.
The Link Control 2 register is missing macros for Target Link Speeds. Add
those in.
Signed-off-by: Frederick Lawler <fred@xxxxxxxxxxxx>
[bhelgaas: use "GT" instead of "GB"]
Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
Signed-off-by: Marek Behún <kabel@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
include/uapi/linux/pci_regs.h | 5 +++++
1 file changed, 5 insertions(+)
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -654,6 +654,11 @@
#define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 /* Supported Speed 8.0GT/s */
#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
+#define PCI_EXP_LNKCTL2_TLS 0x000f
+#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
+#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
+#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
+#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
Patches currently in stable-queue which might be from kabel@xxxxxxxxxx are
queue-4.14/pci-aardvark-move-pcie-reset-card-code-to-advk_pcie_train_link.patch
queue-4.14/pci-aardvark-introduce-an-advk_pcie_valid_device-helper.patch
queue-4.14/pci-aardvark-update-comment-about-disabling-link-training.patch
queue-4.14/pci-aardvark-train-link-immediately-after-enabling-training.patch
queue-4.14/arm64-dts-marvell-armada-37xx-declare-pcie-reset-pin.patch
queue-4.14/pci-aardvark-replace-custom-macros-by-standard-linux-pci_regs.h-macros.patch
queue-4.14/pci-aardvark-fix-a-leaked-reference-by-adding-missing-of_node_put.patch
queue-4.14/pci-aardvark-fix-pcie-max-payload-size-setting.patch
queue-4.14/pinctrl-armada-37xx-correct-pwm-pins-definitions.patch
queue-4.14/arm64-dts-marvell-armada-37xx-set-pcie_reset_pin-to-gpio-function.patch
queue-4.14/pci-aardvark-configure-pcie-resources-from-ranges-dt-property.patch
queue-4.14/pci-aardvark-improve-link-training.patch
queue-4.14/pci-aardvark-fix-link-training.patch
queue-4.14/pci-aardvark-fix-checking-for-link-up-via-ltssm-state.patch
queue-4.14/pci-aardvark-issue-perst-via-gpio.patch
queue-4.14/pinctrl-armada-37xx-correct-mpp-definitions.patch
queue-4.14/pci-add-pci_exp_lnkctl2_tls-macros.patch
queue-4.14/pci-aardvark-wait-for-endpoint-to-be-ready-before-training-link.patch
queue-4.14/pinctrl-armada-37xx-add-missing-pin-pcie1-wakeup.patch
queue-4.14/pci-aardvark-fix-compilation-on-s390.patch
queue-4.14/pci-aardvark-fix-i-o-space-page-leak.patch
queue-4.14/pci-aardvark-don-t-touch-pcie-registers-if-no-card-connected.patch
queue-4.14/pci-aardvark-remove-pcie-outbound-window-configuration.patch
queue-4.14/pci-aardvark-indicate-error-in-val-when-config-read-fails.patch
