This is a note to let you know that I've just added the patch titled
clk: socfpga: agilex: fix up s2f_user0_clk representation
to the 5.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
clk-socfpga-agilex-fix-up-s2f_user0_clk-representation.patch
and it can be found in the queue-5.14 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From f817c132db679d492d96c60993fa2f2c67ab18d0 Mon Sep 17 00:00:00 2001
From: Dinh Nguyen <dinguyen@xxxxxxxxxx>
Date: Tue, 13 Jul 2021 09:46:20 -0500
Subject: clk: socfpga: agilex: fix up s2f_user0_clk representation
From: Dinh Nguyen <dinguyen@xxxxxxxxxx>
commit f817c132db679d492d96c60993fa2f2c67ab18d0 upstream.
Correct the s2f_user0_mux clock representation.
Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Kris Chaplin <kris.chaplin@xxxxxxxxx>
Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20210713144621.605140-2-dinguyen@xxxxxxxxxx
Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/clk/socfpga/clk-agilex.c | 9 +++++++++
1 file changed, 9 insertions(+)
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -195,6 +195,13 @@ static const struct clk_parent_data sdmm
.name = "boot_clk", },
};
+static const struct clk_parent_data s2f_user0_mux[] = {
+ { .fw_name = "s2f_user0_free_clk",
+ .name = "s2f_user0_free_clk", },
+ { .fw_name = "boot_clk",
+ .name = "boot_clk", },
+};
+
static const struct clk_parent_data s2f_user1_mux[] = {
{ .fw_name = "s2f_user1_free_clk",
.name = "s2f_user1_free_clk", },
@@ -319,6 +326,8 @@ static const struct stratix10_gate_clock
4, 0x98, 0, 16, 0x88, 3, 0},
{ AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C,
5, 0, 0, 0, 0x88, 4, 4},
+ { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, ARRAY_SIZE(s2f_user0_mux), 0, 0x24,
+ 6, 0, 0, 0, 0x30, 2, 0},
{ AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C,
6, 0, 0, 0, 0x88, 5, 0},
{ AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C,
Patches currently in stable-queue which might be from dinguyen@xxxxxxxxxx are
queue-5.14/clk-socfpga-agilex-fix-up-s2f_user0_clk-representation.patch
queue-5.14/clk-socfpga-agilex-fix-the-parents-of-the-psi_ref_clk.patch
queue-5.14/clk-socfpga-agilex-add-the-bypass-register-for-s2f_usr0-clock.patch
