This is a note to let you know that I've just added the patch titled clk: socfpga: agilex: fix the parents of the psi_ref_clk to the 5.14-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: clk-socfpga-agilex-fix-the-parents-of-the-psi_ref_clk.patch and it can be found in the queue-5.14 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From 9d563236cca43fc4fe190b3be173444bd48e2a3b Mon Sep 17 00:00:00 2001 From: Dinh Nguyen <dinguyen@xxxxxxxxxx> Date: Tue, 13 Jul 2021 09:46:19 -0500 Subject: clk: socfpga: agilex: fix the parents of the psi_ref_clk From: Dinh Nguyen <dinguyen@xxxxxxxxxx> commit 9d563236cca43fc4fe190b3be173444bd48e2a3b upstream. The psi_ref_clk comes from the C2 node of the main_pll and periph_pll, not the C3. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@xxxxxxxxxxxxxxx Signed-off-by: Kris Chaplin <kris.chaplin@xxxxxxxxx> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx> Link: https://lore.kernel.org/r/20210713144621.605140-1-dinguyen@xxxxxxxxxx Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/clk/socfpga/clk-agilex.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -107,10 +107,10 @@ static const struct clk_parent_data gpio }; static const struct clk_parent_data psi_ref_free_mux[] = { - { .fw_name = "main_pll_c3", - .name = "main_pll_c3", }, - { .fw_name = "peri_pll_c3", - .name = "peri_pll_c3", }, + { .fw_name = "main_pll_c2", + .name = "main_pll_c2", }, + { .fw_name = "peri_pll_c2", + .name = "peri_pll_c2", }, { .fw_name = "osc1", .name = "osc1", }, { .fw_name = "cb-intosc-hs-div2-clk", Patches currently in stable-queue which might be from dinguyen@xxxxxxxxxx are queue-5.14/clk-socfpga-agilex-fix-up-s2f_user0_clk-representation.patch queue-5.14/clk-socfpga-agilex-fix-the-parents-of-the-psi_ref_clk.patch queue-5.14/clk-socfpga-agilex-add-the-bypass-register-for-s2f_usr0-clock.patch