On Tue, 19 Jun 2018, Ricardo Neri wrote: > On Sat, Jun 16, 2018 at 03:24:49PM +0200, Thomas Gleixner wrote: > > The status register is useless in case of MSI. MSI is edge triggered .... > > > > The only register which gives you proper information is the counter > > register itself. That adds an massive overhead to each NMI, because the > > counter register access is synchronized to the HPET clock with hardware > > magic. Plus on larger systems, the HPET access is cross node and even > > slower. > > It starts to sound that the HPET is too slow to drive the hardlockup detector. > > Would it be possible to envision a variant of this implementation? In this > variant, the HPET only targets a single CPU. The actual hardlockup detector > is implemented by this single CPU sending interprocessor interrupts to the > rest of the CPUs. And these IPIs must be NMIs which need to have a software based indicator that the watchdog needs to be checked, which is going to create yet another can of race conditions and in the worst case 'unknown NMI' splats. Not pretty either. Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
