Re: Sun4c interrupt controller, MMU, IOMMU?

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From: "Blue Swirl" <blauwirbel@xxxxxxxxx>
Date: Sun, 12 Aug 2007 11:21:30 +0300

> On 8/12/07, David Miller <davem@xxxxxxxxxxxxx> wrote:
> > > Specifically, how are the interrupts routed, which interrupts (ZS,
> > > ESP, Lance, timers, floppy, cgthree) go through the interrupt
> > > controller?
> >
> > There is no interrupt controller, the individual devices and
> > SBUS slot interrupt sources are wired up directly to the cpu.
> 
> Then what device is poked by arch/sparc/kernel/sun4c_irq.c, I thought
> this was the controller?

It's similar to an interrupt controller, and it can mask certain
interrupts.
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