Mark Hahn wrote: ...
I'm also experimenting with this patch to see if the xor hardwire for modern intel/AMD architectures is still valid. With the old processor p5_mmx was always picked and always within a few MB/s. The new XP is all over the map.
this choice (using pIII_sse even if there's a faster alternative)
is made because it doesn't dirty the cache. are you suggesting that whole-system performance is better with p5_mmx, even though or *because*
the blocks are then in cache? seems unlikley to me, since the checksum
is only used on writes or degraded mode. having written blocks in cache
seems worthless, almost...
I'm an experimentor, not a theorist. I am running a series of experiments to determine if, and by how much, the xor algorithm in include/asm-<arch>/xor.h influences RAID5 write performance and reconstruction.
I'll post results.
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