On Wed, Apr 05, 2017 at 03:54:19PM -0700, Kuppuswamy Sathyanarayanan wrote: > According to Broxton APL PMC spec, gcr mem region starts > at offset 0x1000 from ipc mem base address. In this driver, > PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR > memory region from IPC mem region. So we should use 0x1000(4K) > as GCR offset. But currently this driver uses 0x1008 as GCT Typo, GCT -> GCR. I think we still need to maintain consistency in the commit message. Consider the below message and update if you'd like to. On BXT SoC the PMC MMIO resources for the Global Control Registers (GCR) are located at 4k offset from the IPC1 base. The PLAT_RESOURCE_GCR_OFFSET macro used in this driver is misleading as 0x1008 is the location for PMC_CFG register and not the GCR Base itself. GCR Base = IPC1 Base + 0x1000. This patch updates the GCR Base address correctly. > offset.This patch fixes this issue. > > Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@xxxxxxxxxxxxxxx> > --- > drivers/platform/x86/intel_pmc_ipc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > Changes since v5: > * None > > Changes since v4: > * None > > Changes since v3: > * Updated the commit history > > diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c > index 0651d47..0a33592 100644 > --- a/drivers/platform/x86/intel_pmc_ipc.c > +++ b/drivers/platform/x86/intel_pmc_ipc.c > @@ -82,7 +82,7 @@ > /* exported resources from IFWI */ > #define PLAT_RESOURCE_IPC_INDEX 0 > #define PLAT_RESOURCE_IPC_SIZE 0x1000 > -#define PLAT_RESOURCE_GCR_OFFSET 0x1008 > +#define PLAT_RESOURCE_GCR_OFFSET 0x1000 > #define PLAT_RESOURCE_GCR_SIZE 0x1000 > #define PLAT_RESOURCE_BIOS_DATA_INDEX 1 > #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2 > -- > 2.7.4 > -- Best Regards, Rajneesh
