Mea Culpa. There is a mistake in my example for SDR vs DDR vs DDR2. This is what I get for posting before my morning coffee. The base latency for all of the memory types is that of the base clock rate; 200MHz= 5ns in my given examples. I double factored, making DDR and DDR2 worse than they actually are. Again, my apologies. Ron -----Original Message----- >From: Ron Peacetree <rjpeace@xxxxxxxxxxxxx> >Sent: Apr 26, 2006 8:40 AM >To: mark@xxxxxxxxxxxxxx, pgsql-performance@xxxxxxxxxxxxxx >Subject: Re: [PERFORM] Large (8M) cache vs. dual-core CPUs > >I'm posting this to the entire performance list in the hopes that it will be generally useful. >=r <snip> > >Note also what happens when transferring the first datum after a lull period. >For purposes of example, let's pretend that we are talking about a base clock rate of 200MHz= 5ns. > >The SDR still transfers data every 5ns no matter what. >The DDR transfers the 1st datum in 10ns and then assuming there are at least 2 sequential datums to be >transferred will transfer the 2nd and subsequent sequential pieces of data every 2.5ns. >The DDR2 transfers the 1st datum in 20ns and then assuming there are at least 4 sequential datums to be >transferred will transfer the 2nd and subsequent sequential pieces of data every 1.25ns. > =5= ns to first transfer in all 3 casess. Bad Ron. No Biscuit! > >Thus we can see that randomly accessing RAM degrades performance significantly for DDR and DDR2. We can >also see that the conditions for optimal RAM performance become more restrictive as we go from SDR to DDR to >DDR2. >The reason DDR2 with a low base clock rate excelled at tasks like streaming multimedia and stank at things like >small transaction OLTP DB applications is now apparent. > >Factors like CPU prefetching and victim buffers can muddy this picture a bit. >Also, if the CPU's off die IO is slower than the RAM it is talking to, how fast that RAM is becomes unimportant. > These statements, and everything else I posted, are accurate.
