On Fri, Jul 02, 2021 at 08:08:26PM +0900, Akira Yokosawa wrote:
> Fixes: b97d9921b0fd ("acronym: future/htm: Tag TM, HTM, STM, and RCU via acronym dictionary")
> Fixes: de25a117a9c6 ("index: Add index and acronym tags, take one")
> Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx>
> ---
> Hi again,
>
> I said:
>
> > I'm thinking of adding some rules in the check script to catch
> > this sort of typo.
>
> , and a tentative script caught two other typos.
>
> This v2 patch fixes three typos at once.
>
> Updated check script will be posted later along with other punctuation
> convention fixes.
Queued and pushed, thank you!
Thanx, Paul
> Thanks, Akira
> --
> future/htm.tex | 4 ++--
> summary.tex | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/future/htm.tex b/future/htm.tex
> index dc67ba23..7458f436 100644
> --- a/future/htm.tex
> +++ b/future/htm.tex
> @@ -150,7 +150,7 @@ HTM is therefore a very real possibility for large non-partitionable
> data structures, at least assuming relatively small updates.
>
> \QuickQuiz{
> - Why are relatively small updates important to IXacr{htm} performance
> + Why are relatively small updates important to \IXacr{htm} performance
> and scalability?
> }\QuickQuizAnswer{
> The larger the updates, the greater the probability of conflict,
> @@ -252,7 +252,7 @@ write~\cite{RaviRajwar2012TSX}.
> schemes~\cite{CScottAnanian2006,KevinEMoore2006}
> use DRAM as an extremely large victim cache, but integrating such schemes
> into a production-quality
> -IXalt{cache-coherence}{cache coherence} mechanism is still an unsolved
> +\IXalt{cache-coherence}{cache coherence} mechanism is still an unsolved
> problem.
> In addition, use of DRAM as a victim cache may have unfortunate
> performance and energy-efficiency consequences, particularly
> diff --git a/summary.tex b/summary.tex
> index 63187998..2ed43920 100644
> --- a/summary.tex
> +++ b/summary.tex
> @@ -86,7 +86,7 @@ And that goes at least double for concurrent code.
> where combining concurrency mechanisms with each other or with other
> design tricks can greatly ease parallel programmers' lives.
> \Cref{sec:advsync:Advanced Synchronization} looked at advanced
> -synchronization methods, including lockless programming, IXacrl{nbs},
> +synchronization methods, including lockless programming, \IXacrl{nbs},
> and parallel real-time computing.
> \Cref{chp:Advanced Synchronization: Memory Ordering} dug into the
> critically important topic of memory ordering, presenting techniques
> --
> 2.17.1
>
>
