Re: Possible update candidate in whymb

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On Sat, Mar 20, 2021 at 11:23:36AM +0900, Akira Yokosawa wrote:
> Hi Paul,
> 
> In Appendix C, which you have not updated for a while,
> there is a statement made in commit bb869fd89bfd ("Add
> caution about cache coherence and I/O for new-to-SMP
> architectures") more than a decade ago, which might
> be an update candidate.
> 
> Thoughts?
> 
>         Thanks, Akira
> 
> ------
> diff --git a/appendix/whymb/whymemorybarriers.tex b/appendix/whymb/whymemorybarriers.tex
> index 868758a4..284d48f4 100644
> --- a/appendix/whymb/whymemorybarriers.tex
> +++ b/appendix/whymb/whymemorybarriers.tex
> @@ -1639,7 +1639,7 @@ future such problems:
>         It is my painful duty to inform you that as embedded systems
>         move to multicore architectures, we will no doubt see a fair
>         number of such problems arise.
> -       Hopefully these problems will clear up by the year 2015.
> +       Hopefully these problems will clear up by the year 202x.

Good catch!  I queued the commit shown below.

							Thanx, Paul

------------------------------------------------------------------------

commit bd77de3dd7a09e189cda3c6da75628da7fbd4d88
Author: Paul E. McKenney <paulmck@xxxxxxxxxx>
Date:   Fri Mar 19 21:06:56 2021 -0700

    whymb: Fix outdated date
    
    The year 2015 is no longer in the future.
    
    Reported-by: Akira Yokosawa <akiyks@xxxxxxxxx>
    Signed-off-by: Paul E. McKenney <paulmck@xxxxxxxxxx>

diff --git a/appendix/whymb/whymemorybarriers.tex b/appendix/whymb/whymemorybarriers.tex
index 868758a..dc9bd04 100644
--- a/appendix/whymb/whymemorybarriers.tex
+++ b/appendix/whymb/whymemorybarriers.tex
@@ -1639,7 +1639,10 @@ future such problems:
 	It is my painful duty to inform you that as embedded systems
 	move to multicore architectures, we will no doubt see a fair
 	number of such problems arise.
-	Hopefully these problems will clear up by the year 2015.
+	By the year 2021, there were some efforts to address
+	these problems with new interconnect standards, with some
+	debate as to how effective these standards will really
+	be~\cite{WilliamGWong2019CCIX-CXL}.
 
 \item	Device interrupts that ignore cache coherence.
 



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