Hi Paul,
In Appendix C, which you have not updated for a while,
there is a statement made in commit bb869fd89bfd ("Add
caution about cache coherence and I/O for new-to-SMP
architectures") more than a decade ago, which might
be an update candidate.
Thoughts?
Thanks, Akira
------
diff --git a/appendix/whymb/whymemorybarriers.tex b/appendix/whymb/whymemorybarriers.tex
index 868758a4..284d48f4 100644
--- a/appendix/whymb/whymemorybarriers.tex
+++ b/appendix/whymb/whymemorybarriers.tex
@@ -1639,7 +1639,7 @@ future such problems:
It is my painful duty to inform you that as embedded systems
move to multicore architectures, we will no doubt see a fair
number of such problems arise.
- Hopefully these problems will clear up by the year 2015.
+ Hopefully these problems will clear up by the year 202x.
