[PATCH 13/14] advsync: Use pseudo asm in sequence in 'Data Dependency Barriers'

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>From 2b779ea16b0185b121063faa0ca534a75d67fc8d Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@xxxxxxxxx>
Date: Sun, 16 Apr 2017 16:14:24 +0900
Subject: [PATCH 13/14] advsync: Use pseudo asm in sequence in 'Data Dependency Barriers'

Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx>
---
 advsync/memorybarriers.tex | 33 +++++++++++++++++----------------
 1 file changed, 17 insertions(+), 16 deletions(-)

diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index 2b36214..9b878f3 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -1622,8 +1622,8 @@ Section~\ref{sec:advsync:Device Operations}).
 	\begin{minipage}[t]{\columnwidth}
 	\small
 	\begin{verbatim}
-	a = 1;
-	b = 1;
+	STORE a = 1
+	STORE b = 1
 	<write barrier>
 	\end{verbatim}
 	\end{minipage}
@@ -1673,7 +1673,8 @@ of the confines of a given architecture:
 
 The usage requirements of data dependency barriers are a little subtle, and
 it's not always obvious that they're needed.  To illustrate, consider the
-following sequence of events, with initial values
+following sequence of events (in pseudo asm), with initial values of shared
+variables
 {\tt \{A~=~1, B~=~2, C~=~3, P~=~\&A, Q~=~\&C\}}:
 
 \vspace{5pt}
@@ -1681,13 +1682,13 @@ following sequence of events, with initial values
 \tt
 \scriptsize
 \begin{tabular}{l|l}
-	\nf{CPU 1} &	\nf{CPU 2} \\
+	\nf{CPU 1}	& \nf{CPU 2} \\
 	\hline
-	B = 4; & \\
-	<write barrier> & \\
-	P = \&B; &	\\
-		&	Q = P; \\
-		&	D = *Q; \\
+	STORE B = 4	& \\
+	<write barrier>	& \\
+	STORE P = \&B	& \\
+			& Q = LOAD P \\
+			& D = LOAD *Q \\
 \end{tabular}
 \end{minipage}
 \vspace{5pt}
@@ -1734,14 +1735,14 @@ address load and the data load (again with initial values of
 \tt
 \scriptsize
 \begin{tabular}{l|p{1.5in}}
-	\nf{CPU 1} &	\nf{CPU 2} \\
+	\nf{CPU 1}	& \nf{CPU 2} \\
 	\hline
-	B = 4; & \\
-	<write barrier> & \\
-	P = \&B; &	\\
-		&	Q = P; \\
-		&	<data dependency barrier> \\
-		&	D = *Q; \\
+	STORE B = 4	& \\
+	<write barrier>	& \\
+	STORE P = \&B	& \\
+			& Q = LOAD P \\
+			& <data dependency barrier> \\
+			& D = LOAD *Q \\
 \end{tabular}
 \end{minipage}
 \vspace{5pt}
-- 
2.7.4


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