[PATCH 09/14] advsync: Use READ_ONCE()/WRITE_ONCE() in sequence of 'Device Operations'

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>From 20904d88784deb41bfb853b198017eca6a058bc8 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@xxxxxxxxx>
Date: Sun, 16 Apr 2017 23:44:56 +0900
Subject: [PATCH 09/14] advsync: Use READ_ONCE()/WRITE_ONCE() in sequence of 'Device Operations'

Using pseudo-asm code here results in a redundant look. In this
section, using READ_ONCE()/WRITE_ONCE() in code sequence gives
a good contrast with the resulting ordering of memory accesses.

Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx>
---
 advsync/memorybarriers.tex | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index 7b50511..f94b113 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -1261,15 +1261,15 @@ Some devices present their control interfaces as collections of memory
 locations, but the order in which the control registers are accessed is very
 important.  For instance, imagine an Ethernet card with a set of internal
 registers that are accessed through an address port register~(A) and a data
-port register~(D).  To read internal register~5, the following code might then
-be used:
+port register~(D).  To read internal register~5, the following code (in C)
+might then be used:
 
 \vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
-*A = 5;
-x = *D;
+WRITE_ONCE(*A, 5);
+x = READ_ONCE(*D);
 \end{verbatim}
 \vspace{1pt}
 \end{minipage}
-- 
2.7.4


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