>From 827f6c65b5fbae89edab6b86b70d39a7582d708d Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@xxxxxxxxx>
Date: Sun, 16 Apr 2017 08:15:26 +0900
Subject: [PATCH 08/14] advsync: Add footnote to imply necessity of data dependency barrier
Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx>
---
advsync/memorybarriers.tex | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index 8173684..7b50511 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -1244,7 +1244,15 @@ following results are possible:
\vspace{5pt}
Note that CPU~2 will never try and load~C into~D because the CPU will load~P
-into~Q before issuing the load of~*Q.
+into~Q before issuing the load of~*Q.\footnote{Although it might sound
+ counterintuitive, one of the results,
+ {\tt\scriptsize (Q~==~\&B) and (D~==~2)},
+ does not necessarily mean that CPU~1's
+ {\tt\scriptsize STORE B~=~4} was issued
+ {\em after} {\tt\scriptsize STORE P~=~\&B}.
+ To reach a consensus in ordering, we need a pair of memory barriers
+ as is described in
+ Section~\ref{sec:advsync:Data Dependency Barriers}.}
\subsection{Device Operations}
\label{sec:advsync:Device Operations}
--
2.7.4
--
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