>From 81c2ce55ce99ede156f407c869b18289366917e4 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@xxxxxxxxx>
Date: Sun, 16 Apr 2017 00:01:10 +0900
Subject: [PATCH 03/14] advsync: Use pseudo asm in sequence in 'Review of Locking Impl'
Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx>
---
advsync/memorybarriers.tex | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index 173380a..299c436 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -1060,16 +1060,16 @@ the sequence of operations might be as follows:
\begin{minipage}[t]{\columnwidth}
\tt \scriptsize
\begin{tabular}{l|l}
- \nf{CPU 1} & \nf{CPU 2} \\
+ \nf{CPU 1} & \nf{CPU 2} \\
\hline
- (critical section) & \tco{atomic_xchg(&lck->a, 1)->1} \\
- \tco{smp_mb();} & lck->a->1 \\
- lck->a=0; & lck->a->1 \\
- & lck->a->0 \\
- & (implicit \tco{smp_mb()} 1) \\
- & \tco{atomic_xchg(&lck->a, 1)->0} \\
- & (implicit \tco{smp_mb()} 2) \\
- & (critical section) \\
+ (critical section) & \tco{atomic_xchg(&lck->a, 1)} $\rightarrow$1 \\
+ <memory barrier> & LOAD lck->a $\rightarrow$1 \\
+ STORE lck->a = 0 & LOAD lck->a $\rightarrow$1 \\
+ & LOAD lck->a $\rightarrow$0 \\
+ & (implicit memory barrier \#1) \\
+ & \tco{atomic_xchg(&lck->a, 1)} $\rightarrow$0 \\
+ & (implicit memory barrier \#2) \\
+ & (critical section) \\
\end{tabular}
\end{minipage}
\vspace{5pt}
--
2.7.4
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