>From ca4c666a7c30440610ce148f73960c2e21030a56 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@xxxxxxxxx>
Date: Sat, 15 Apr 2017 23:41:35 +0900
Subject: [PATCH 02/14] advsync: Substitute READ_ONCE()/WRITE_ONCE() for ACCESS_ONCE()
Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx>
---
advsync/memorybarriers.tex | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index d82a968..173380a 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -490,7 +490,7 @@ CPUs' accesses are to one single variable.
In this single-variable case, cache coherence guarantees the
global ordering, at least assuming that some of the more aggressive
compiler optimizations are disabled via the Linux kernel's
-\co{ACCESS_ONCE()} directive or C++11's relaxed
+\co{READ_ONCE()} and \co{WRITE_ONCE()} directives or C++11's relaxed
atomics~\cite{PeteBecker2011N3242}.
In contrast, if there are multiple variables, memory barriers are
required for the CPUs to consistently agree on the order for current
--
2.7.4
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