Signed-off-by: SeongJae Park <sj38.park@xxxxxxxxx>
---
formal/ppcmem.tex | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/formal/ppcmem.tex b/formal/ppcmem.tex
index 9e0392a..c18cb9a 100644
--- a/formal/ppcmem.tex
+++ b/formal/ppcmem.tex
@@ -165,7 +165,7 @@ exclusive'' in ARM parlance and ``load reserve'' in Power parlance)
and store-conditional (``store register exclusive'' in ARM parlance),
respectively. When these are used together, they form an atomic
instruction sequence, roughly similar to the compare-and-swap sequences
-exemplified by the x86 co{lock;cmpxchg} instruction. Moving to a higher
+exemplified by the x86 \co{lock;cmpxchg} instruction. Moving to a higher
level of abstraction, the sequence from lines~10-15 is equivalent to
the Linux kernel's \co{atomic_add_return(&z, 0)}. Finally, line~16 is
roughly equivalent to the C statement \co{r3=y}.
--
2.10.0
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