Hello linux experts and users, When I analyze https://elixir.bootlin.com/linux/v5.15.68/source/drivers/pci/controller/dwc/ pcie-designware-ep.c#L777, The struct dw_pcie_ep contains a member msi_mem and the driver generates msi interrupt by writing the given data at that address. (see line 533 of the dw_pcie_ep_raise_msi_irq function) So that address (ep->msi_mem) is the host address (probably GICV3's ITS's GITS_TRANSLATER register address) that the host has told the endpoint. But when I trace the code how the msi_mem (virtual address) is decided, I see (in processing order in the dw_pcie_ep_init function) : res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); ep->phys_base = res->start; ep->addr_size = resource_size(res); ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size, ep->page_size); ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys, epc->mem->window.page_size); the allocate function allocates some port of the "addr_space" range and returns the virtual address (and fills the second argument with physical address). Then is this 'addr_space' filled by the boot loader? How can I know the host's ITS register range seen from the endpoint? (I mean the host PCI bridge will have a translation function that converts upstream PCI address --> host CPU's physical address, or IO virtual address if the host uses IOMMU betwen the PCIe and ITS). Any comment will be really appreciated. Thank you! Chan Kim _______________________________________________ Kernelnewbies mailing list Kernelnewbies@xxxxxxxxxxxxxxxxx https://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
