Hi, I have a question about dmb barriers in arm64's head.S. In the head.S, I could see the pattern below several times. str w0, [x1] dmb sys dc ivac, x1 // Invalidate potentially stale cache line I found that, Commit(fix cache flushing and barriers in set_cpu_boot_mode_flag) explained the code. > This patch reworks the broken flushing code so that we: > > (1) Use a DMB to order the strongly-ordered write of the cacheline > against the subsequent cache-maintenance operation (by-VA > operations only hazard against normal, cacheable accesses). > > (2) Use a single dc ivac instruction to invalidate any clean lines > containing a stale copy of the line after it has been updated. > Use a DMB to order the strongly-> ordered write of the cacheline But I can't understand why the store operation should precede the dc operation. Is there any problem, if the dc operation precedes the store operation? _______________________________________________ Kernelnewbies mailing list Kernelnewbies@xxxxxxxxxxxxxxxxx https://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
