How can I ever thank you?
Sent from my iPhone
> On Sep 4, 2020, at 3:00 PM, Marlon Rac Cambasis <marlonrc08@xxxxxxxxx> wrote:
>
> Hello, I would like to make my first contribution to the Linux kernel in the
> form of a (trivial) spelling fix. Does this patch (including the subject and the
> way my mail is being displayed), meet the requirements? Furthermore, I think the
> correct place to send it to would be devicetree@xxxxxxxxxxxxxxx and also CCing
> it to trivial@xxxxxxxxxx. Is this all okay? Should I send it to somewhere else,
> do I need to make any changes? Also I don't need to add a body to the patch
> when I send it do I?
>
> Here is my patch:
>
> Signed-off-by: Marlon Rac Cambasis <marlonrc08@xxxxxxxxx>
> ---
> Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt | 2 +-
> Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt | 2 +-
> Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> index 70659c9..372f473 100644
> --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt
> @@ -75,7 +75,7 @@ Required Properties:
> The child node should contain a list of pin(s) on which a particular pin
> function selection or pin configuration (or both) have to applied. This
> list of pins is specified using the property name "samsung,pins". There
> - should be atleast one pin specfied for this property and there is no upper
> + should be atleast one pin specified for this property and there is no upper
> limit on the count of pins that can be specified. The pins are specified
> using pin names which are derived from the hardware manual of the SoC. As
> an example, the pins in GPA0 bank of the pin controller can be represented
> diff --git a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> index 6e80270..17b7a6a 100644
> --- a/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> +++ b/Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
> @@ -9,7 +9,7 @@ Optional property:
> - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
> NPCM7xx contain four software reset that represent numbers 1 to 4.
>
> - If 'nuvoton,sw-reset-number' is not specfied software reset is disabled.
> + If 'nuvoton,sw-reset-number' is not specified software reset is disabled.
>
> Example:
> rstc: rstc@f0801000 {
> diff --git a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
> index d78d4a8f..a819763 100644
> --- a/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
> +++ b/Documentation/devicetree/bindings/watchdog/aspeed-wdt.txt
> @@ -20,7 +20,7 @@ Optional properties:
> This is useful in situations where another watchdog engine on chip is
> to perform the reset.
>
> - If 'aspeed,reset-type=' is not specfied the default is to enable system
> + If 'aspeed,reset-type=' is not specified the default is to enable system
> reset.
>
> Reset types:
> --
> 2.9.0
>
>
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