Hi all,
I'm trying to build a kernel module by statically linking object files
with a library. My source tree looks like this:
source/
├── bar/
| ├── bar1.c
| └── bar2.c
└── foo.c
The relevant parts of my Makefile look like this:
mydriver-y := foo.o bar.a
obj-m += mydriver.o
bar-objs := bar/bar1.o bar/bar2.o
# This builds foo.o
mydriver:
$(MAKE) -C $(kernel-src-dir) M=$(CURDIR) modules
$(bar-objs): %.o: %.c
$(MAKE) -C $(kernel-src-dir) M=$(CURDIR) $@
bar.a: $(bar-objs)
ar rcs $@ $^
Here, the rule for $(bar-objs) should use the kbuild machinery to
build bar1.o and bar2.o, as stated in Documentation/kbuld/modules.txt:
--- 2.4 Building Separate Files
It is possible to build single files that are part of a module.
This works equally well for the kernel, a module, and even for
external modules.
Example (The module foo.ko, consist of bar.o and baz.o):
make -C $KDIR M=$PWD bar.lst
make -C $KDIR M=$PWD baz.o
make -C $KDIR M=$PWD foo.ko
make -C $KDIR M=$PWD /
However, when I try to build bar.a, I get the following:
make -C /lib/modules/$(uname -r)/build M=/home/martin/source/bar/bar1.o
make[1]: Entering directory '/usr/src/linux-headers-4.13.0-38-generic'
scripts/Makefile.build:44: /home/martin/source/bar/Makefile: No such
file or directory
make[2]: *** No rule to make target '/home/martin/source/bar/Makefile'. Stop.
It's like kbuild expects me to have a Makefile on the 'bar' subdir as
well. Am I doing something wrong?
PS: Yes, I'm aware I could just add $(bar-objs) to mydriver-y and
avoid building bar.a, but I really need to have those files as a
separate library. Building them with a separate Makefile (i.e. without
the kbuild machinery) isn't desirable either because I want to use the
full array of flags and such that kbuild adds when invoking gcc.
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