>Try below points:
>1. I am not sure about snapdragon(is it Qualcomm?) but try
>CONFIG_CPU_DCACHE_DISABLE.
>1. I am not sure about snapdragon(is it Qualcomm?) but try
>CONFIG_CPU_DCACHE_DISABLE.
I did that already, device is not booting. In our architecture cache is tightly coupled with CPU.
>2. You are better off programming some DMA master to do large (and
>uncached) reads/writes to RAM and timing that.
>uncached) reads/writes to RAM and timing that.
DMA is not a standard way, i suppose, as it depends on what I/O peripheral we are doing the DMA.
>You should always add arm mailing list and please mention the chip set details.
>cat /proc/cpuinfo is a great way
>cat /proc/cpuinfo is a great way
Processor : ARMv7 Processor rev 2 (v7l)
BogoMIPS : 163.38
Features : swp half thumb fastmult vfp edsp neon vfpv3 tls
CPU implementer : 0x51
CPU architecture: 7
CPU variant : 0x1
CPU part : 0x00f
CPU revision : 2
Thanks
Sandeep
On Wed, Feb 27, 2013 at 5:37 PM, anish singh <anish198519851985@xxxxxxxxx> wrote:
> Hi AllTry below points:
> In performance benchmark tools, When we profile read/write timings mostly,
> those read/writes are done to cache only.
>
> I want to measure my DDR(RAM chip) performance.
> So i want to make sure, every read/write should happen to DDR RAM chip only.
1. I am not sure about snapdragon(is it Qualcomm?) but try
CONFIG_CPU_DCACHE_DISABLE.
2. You are better off programming some DMA master to do large (and
uncached) reads/writes to RAM and timing that.
However simple uncached LDR/STR from the CPU may not be a great
measure of RAM controller perf.
You should always add arm mailing list and please mention the chip set details.
cat /proc/cpuinfo is a great way
>
> How can i achieve this...Any ideas/suggestions...?
>
> --
> With regards,
> Sandeep Kumar Anantapalli,
>
> _______________________________________________
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> Kernelnewbies@xxxxxxxxxxxxxxxxx
> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
>
With regards,
Sandeep Kumar Anantapalli,
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