yeah, i think the page size refer to hardware mechanism. reference as "Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A: System Programming Guide, Part 1" "When paging is used, the processor divides the linear address space into fixed-size pages (of 4 KBytes, 2 MBytes, or 4 MBytes in length) that can be mapped into physical memory and/or disk storage. When a program (or task) references a logical address in memory, the processor translates the address into a linear address and then uses its paging mechanism to translate the linear address into a corresponding physical address." "The PSE flag enables large page sizes: 4-MByte pages or 2-MByte pages (when the PAE flag is set). When the PSE flag is clear, the more common page length of 4 KBytes is used. See Section 3.7.2, “Linear Address Translation (4-MByte Pages)”, Section 3.8.3, “Linear Address Translation With PAE Enabled (2-MByte Pages)”, and Section 3.9, “36-Bit Physical Addressing Using the PSE-36 Paging Mechanism” for more information about the use of the PSE flag." "The TLBs store the most recently used page-directory and page-table entries. They speed up memory accesses when paging is enabled by reducing the number of memory accesses that are required to read the page tables stored in system memory. The TLBs are divided into four groups: instruction TLBs for 4-KByte pages, data TLBs for 4-KByte pages; instruction TLBs for large pages (2-MByte or 4-MByte pages), and data TLBs for large pages. The TLBs are normally active only in protected mode with paging enabled. When paging is disabled or the processor is in real-address mode, the TLBs maintain their contents until explicitly or implicitly flushed" i hope this will be helpful. BRs, Lin 2009/5/11 Mulyadi Santosa <mulyadi.santosa@xxxxxxxxx>: > On Mon, May 11, 2009 at 9:53 PM, Sandeep K Sinha > <sandeepksinha@xxxxxxxxx> wrote: >> Does x86 support 8K pages??? >> >> IMO, No. >> >> On Mon, May 11, 2009 at 8:18 PM, Vikash Kumar <vikashskumar@xxxxxxxxx> >> wrote: >>> >>> Dear all, >>> >>> I am trying to increase the default page size (by default 4k) for x86. As >>> I understand I need to modify the PAGE_SHIFT macro in >>> "include/asm-x86/page.h" to achieve this. I changed the default value of 12 >>> to 13 (to make the page size 8K). But when I build the kernel and try to >>> boot using it, I get crash > > Adding what Sandeep has said, 4K is default page size. Other than > that, you're left with 2MB or 4MB page size ...but AFAIK you need to > turn on PSE (page size extension). And probably hugetlb too. > > regards, > > Mulyadi. > > -- > To unsubscribe from this list: send an email with > "unsubscribe kernelnewbies" to ecartis@xxxxxxxxxxxx > Please read the FAQ at http://kernelnewbies.org/FAQ > > -- To unsubscribe from this list: send an email with "unsubscribe kernelnewbies" to ecartis@xxxxxxxxxxxx Please read the FAQ at http://kernelnewbies.org/FAQ
